Leslie Zhai via llvm-dev
2017-Jul-25 08:29 UTC
[llvm-dev] How to migrate x86_sse2_psrl_dq after LLVM v3.8?
Hi LLVM developers,
After Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs
intrinsics. The builtins aren't used by clang.
https://reviews.llvm.org/rL229069 there was no
Intrinsic::x86_sse2_psrl_dq any more, then how to migrate:
Function *F Intrinsic::getDeclaration(TheModule,
Intrinsic::x86_sse2_psrl_dq);
Result Builder.CreateCall(F, ArrayRef<Value
*>(&Ops[0], 2),
"palignr");
And clang v3.9 migrated X86::BI__builtin_ia32_palignr128 like this
https://github.com/llvm-mirror/clang/blob/master/lib/CodeGen/CGBuiltin.cpp#L7629
just ignored the if (shiftVal < 32) condition?
https://github.com/llvm-mirror/clang/blob/release_33/lib/CodeGen/CGBuiltin.cpp#L2642
Please give me some hint, thanks a lot!
--
Regards,
Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/
Craig Topper via llvm-dev
2017-Jul-25 14:30 UTC
[llvm-dev] How to migrate x86_sse2_psrl_dq after LLVM v3.8?
We should still parse IR containing that intrinsic and turn into something equivalent. You can see what that looks like by running it through the opt binary without running any passes. If you're trying to generate IR and you used to generate that intrinsic, you'll need to generate an equivalent shufflevector instruction. You can find code for that in AutoUpgrade.cpp On Tue, Jul 25, 2017 at 1:30 AM Leslie Zhai <lesliezhai at llvm.org.cn> wrote:> Hi LLVM developers, > > After Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs > intrinsics. The builtins aren't used by clang. > https://reviews.llvm.org/rL229069 there was no > Intrinsic::x86_sse2_psrl_dq any more, then how to migrate: > > > Function *F > Intrinsic::getDeclaration(TheModule, > Intrinsic::x86_sse2_psrl_dq); > Result > Builder.CreateCall(F, ArrayRef<Value *>(&Ops[0], 2), > "palignr"); > > > And clang v3.9 migrated X86::BI__builtin_ia32_palignr128 like this > > https://github.com/llvm-mirror/clang/blob/master/lib/CodeGen/CGBuiltin.cpp#L7629 > just ignored the if (shiftVal < 32) condition? > > https://github.com/llvm-mirror/clang/blob/release_33/lib/CodeGen/CGBuiltin.cpp#L2642 > > Please give me some hint, thanks a lot! > > -- > Regards, > Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/ > > --~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170725/87621023/attachment.html>
Leslie Zhai via llvm-dev
2017-Jul-26 03:36 UTC
[llvm-dev] How to migrate x86_sse2_psrl_dq after LLVM v3.8?
Hi Craig, Thanks for your kind response! 在 2017年07月25日 22:30, Craig Topper 写道:> We should still parse IR containing that intrinsic and turn into > something equivalent. You can see what that looks like by running it > through the opt binary without running any passes.I am migrating dragonegg https://reviews.llvm.org/D35667 I will test it without running any PASS.> > If you're trying to generate IR and you used to generate that > intrinsic, you'll need to generate an equivalent shufflevector > instruction. You can find code for that in AutoUpgrade.cppI just grep sse2.psrl.dq in lib/IR/AutoUpgrade.cpp, there is UpgradeX86PSRLDQIntrinsics for x86.sse2.psrl.dq, and emit a shuffle to move the bytes if (Shift < 16), else just return the zero vector Constant::getNullValue https://github.com/llvm-mirror/llvm/blob/master/lib/IR/AutoUpgrade.cpp#L639 so could I migrate dragonegg for the if (ShiftVal < 32) condition like this? https://github.com/xiangzhai/dragonegg/blob/gcc-6_3-branch/src/x86/Target.cpp#L904> > On Tue, Jul 25, 2017 at 1:30 AM Leslie Zhai <lesliezhai at llvm.org.cn > <mailto:lesliezhai at llvm.org.cn>> wrote: > > Hi LLVM developers, > > After Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs > intrinsics. The builtins aren't used by clang. > https://reviews.llvm.org/rL229069 there was no > Intrinsic::x86_sse2_psrl_dq any more, then how to migrate: > > > Function *F > Intrinsic::getDeclaration(TheModule, > Intrinsic::x86_sse2_psrl_dq); > Result > Builder.CreateCall(F, ArrayRef<Value *>(&Ops[0], 2), > "palignr"); > > > And clang v3.9 migrated X86::BI__builtin_ia32_palignr128 like this > https://github.com/llvm-mirror/clang/blob/master/lib/CodeGen/CGBuiltin.cpp#L7629 > just ignored the if (shiftVal < 32) condition? > https://github.com/llvm-mirror/clang/blob/release_33/lib/CodeGen/CGBuiltin.cpp#L2642 > > Please give me some hint, thanks a lot! > > -- > Regards, > Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/ > > -- > ~Craig-- Regards, Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/