Rail Shafigulin via llvm-dev
2016-Jan-21 00:27 UTC
[llvm-dev] a bundle with one instruction
> No. Bundles with single instructions are not allowed, but bundles can be > mixed with instructions that are not bundled. > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >I'm slightly confused. Can you elaborate on what it means to have bundles that are mixed with instructions that are not bundled? What I need for my target is to bundle every instruction, even if it is solo instruction. What would be the best way to achieve this? Current idea is to add a NOP instruction if MI has only one instruction in it. Is it possible? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160120/e19dec67/attachment.html>
Krzysztof Parzyszek via llvm-dev
2016-Jan-21 12:33 UTC
[llvm-dev] a bundle with one instruction
On 1/20/2016 6:27 PM, Rail Shafigulin wrote:> > I'm slightly confused. Can you elaborate on what it means to have > bundles that are mixed with instructions that are not bundled? > > What I need for my target is to bundle every instruction, even if it is > solo instruction. What would be the best way to achieve this? Current > idea is to add a NOP instruction if MI has only one instruction in it. > Is it possible? > > Any help is appreciated.You can have BUNDLE // 2 instructions in a bundle instruction1 // instruction2 // instruction3 // single, non-bundled instruction BUNDLE // another bundle with 2 instructions instruction4 // instruction5 // instruction3 is not bundled with anything, and it's between two other bundles---that's what I meant by "mixing". On Hexagon, on the hardware level, every instruction belongs to some packet, whether it's a packet with one or more instructions. What we do is that we encode single instructions as single-instruction packets, but that happens after the IR is lowered to the MC form. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Rail Shafigulin via llvm-dev
2016-Jan-21 22:53 UTC
[llvm-dev] a bundle with one instruction
You can have> > BUNDLE // 2 instructions in a bundle > instruction1 // > instruction2 // > instruction3 // single, non-bundled instruction > BUNDLE // another bundle with 2 instructions > instruction4 // > instruction5 // > > instruction3 is not bundled with anything, and it's between two other > bundles---that's what I meant by "mixing". > > > On Hexagon, on the hardware level, every instruction belongs to some > packet, whether it's a packet with one or more instructions. What we do is > that we encode single instructions as single-instruction packets, but that > happens after the IR is lowered to the MC form. > > > -Krzysztof > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >Just to clarify, when you say MC form do you mean Hexagon Assembly? Apologies if the question seems silly. I've been working with LLVM only a few months. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160121/cf051213/attachment.html>
Rail Shafigulin via llvm-dev
2016-Jan-22 23:38 UTC
[llvm-dev] a bundle with one instruction
On Thu, Jan 21, 2016 at 4:33 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote:> On 1/20/2016 6:27 PM, Rail Shafigulin wrote: > >> >> I'm slightly confused. Can you elaborate on what it means to have >> bundles that are mixed with instructions that are not bundled? >> >> What I need for my target is to bundle every instruction, even if it is >> solo instruction. What would be the best way to achieve this? Current >> idea is to add a NOP instruction if MI has only one instruction in it. >> Is it possible? >> >> Any help is appreciated. >> > > You can have > > BUNDLE // 2 instructions in a bundle > instruction1 // > instruction2 // > instruction3 // single, non-bundled instruction > BUNDLE // another bundle with 2 instructions > instruction4 // > instruction5 // > > instruction3 is not bundled with anything, and it's between two other > bundles---that's what I meant by "mixing". > > > On Hexagon, on the hardware level, every instruction belongs to some > packet, whether it's a packet with one or more instructions. What we do is > that we encode single instructions as single-instruction packets, but that > happens after the IR is lowered to the MC form. > > > -Krzysztof > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >Just out of curiosity, why Hexagon doesn't create a bundle with a single instruction earlier? Wouldn't it be more consistent (and convinient) to bundle all the instructions in one place (at MachineInstr level) rather then handle it in different places? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160122/60cf5eb3/attachment.html>