llvm dev - Apr 2013 - [LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?

Hi,

Let's say we have a 32-bit architecture where 64-bit additions are done
using 2 operations.

Instructions are defined as follow in TableGen:
   defm ADD64  : ALU32<"add", 1, 1, addc>;
   defm ADD64C : ALU32<"addrc", 1, 2, adde>;


Let's assume that the carry bit is implicit and that the 2 operations must
*always* be stuck together for the 64-bit add to work properly.
Is there a default guarantee that nothing will ever be inserted between
"add" and "addrc" or is there a flag/condition to set
somewhere to have
that guarantee?

Thanks
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On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com>
wrote:
> Hi,
> 
> Let's say we have a 32-bit architecture where 64-bit additions are done
using 2 operations.
> 
> Instructions are defined as follow in TableGen:
>    defm ADD64  : ALU32<"add", 1, 1, addc>;
>    defm ADD64C : ALU32<"addrc", 1, 2, adde>;
> 
> 
> Let's assume that the carry bit is implicit and that the 2 operations
must *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between
"add" and "addrc" or is there a flag/condition to set
somewhere to have that guarantee?
The register allocator expects to be able to insert spill code and copies
between any instructions, except terminators.

The only way around that is to use pseudo-instructions that are expanded after
RA.

/jakob

Hi Francois,

If you model the effect of your carry on the instructions, the scheduler (and
the other backend passes) should ensure that nothing that affects the carry will
be inserted between your two instructions (assuming they are issued with nothing
affecting the carry in between in the first place).
Therefore, you shouldn’t have to force them to be stuck together.

If you still do, what Jakob proposed is what you are looking for.

-Quentin

On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com>
wrote:
> Hi,
> 
> Let's say we have a 32-bit architecture where 64-bit additions are done
using 2 operations.
> 
> Instructions are defined as follow in TableGen:
>    defm ADD64  : ALU32<"add", 1, 1, addc>;
>    defm ADD64C : ALU32<"addrc", 1, 2, adde>;
> 
> 
> Let's assume that the carry bit is implicit and that the 2 operations
must *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between
"add" and "addrc" or is there a flag/condition to set
somewhere to have that guarantee?
> 
> Thanks
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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I really have to force them to stuck together otherwise the carry will just
not work.

How about wrapping the 2 instructions in a bundle?
Would that be a way?
http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles


On Mon, Apr 15, 2013 at 5:24 PM, Quentin Colombet <qcolombet at
apple.com>wrote:
> Hi Francois,
>
> If you model the effect of your carry on the instructions, the scheduler
> (and the other backend passes) should ensure that nothing that affects the
> carry will be inserted between your two instructions (assuming they are
> issued with nothing affecting the carry in between in the first place).
> Therefore, you shouldn’t have to force them to be stuck together.
>
> If you still do, what Jakob proposed is what you are looking for.
>
> -Quentin
>
> On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at
gmail.com> wrote:
>
> Hi,
>
> Let's say we have a 32-bit architecture where 64-bit additions are done
> using 2 operations.
>
> Instructions are defined as follow in TableGen:
>    defm ADD64  : ALU32<"add", 1, 1, addc>;
>    defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>
>
> Let's assume that the carry bit is implicit and that the 2 operations
must
> *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between
> "add" and "addrc" or is there a flag/condition to set
somewhere to have
> that guarantee?
>
> Thanks
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>
>
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Hi Jakob,

If glue operands are used by the scheduler to keep instructions 
together, why can't the register allocator also do this?

Regards,
Sam

On 15/04/2013 23:12, Jakob Stoklund Olesen wrote:
> On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at
gmail.com> wrote:
>
>> Hi,
>>
>> Let's say we have a 32-bit architecture where 64-bit additions are
done using 2 operations.
>>
>> Instructions are defined as follow in TableGen:
>>     defm ADD64  : ALU32<"add", 1, 1, addc>;
>>     defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>>
>>
>> Let's assume that the carry bit is implicit and that the 2
operations must *always* be stuck together for the 64-bit add to work properly.
>> Is there a default guarantee that nothing will ever be inserted between
"add" and "addrc" or is there a flag/condition to set
somewhere to have that guarantee?
> The register allocator expects to be able to insert spill code and copies
between any instructions, except terminators.
>
> The only way around that is to use pseudo-instructions that are expanded
after RA.
>
> /jakob
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev