search for: quentin

Displaying 20 results from an estimated 739 matches for "quentin".

2016 Nov 18
5
LoopStrengthReduce Code Owner: nominating Quentin
I’d like to nominate Quentin Colombet as LSR code owner. He has handled most of the reviews for me for the past couple years (thanks Quentin), and is willing to take on the responsiblity. Frankly, turning over ownership to Quentin is overdue. -Andy
2016 Nov 18
0
LoopStrengthReduce Code Owner: nominating Quentin
> On Nov 17, 2016, at 8:51 PM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I’d like to nominate Quentin Colombet as LSR code owner. He has handled most of the reviews for me for the past couple years (thanks Quentin), and is willing to take on the responsiblity. Frankly, turning over ownership to Quentin is overdue. This also seems pretty obvious to me, and other folks seem to agree. Quentin, assum...
2017 May 30
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Thanks Diana. That is indeed the assumption in the code and this is obviously wrong. Could you try the attached patch? (I haven’t even tried to compile it though) Cheers, -Quentin -------------- next part -------------- A non-text attachment was scrubbed... Name: localizer_tentative_fix.diff Type: application/octet-stream Size: 774 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170530/455d16da/att...
2015 Apr 24
2
[LLVMdev] Multiple connected components in live interval
Hi Jonas, I won’t have time to look at it this week after all. I’ll try to do that next week. If you do not hear back from me by end of next, do not hesitate to ping me! Cheers, -Quentin > On Apr 22, 2015, at 9:32 AM, Quentin Colombet <qcolombet at apple.com> wrote: > >> >> On Apr 21, 2015, at 11:49 PM, Jonas Paulsson <jonas.paulsson at ericsson.com <mailto:jonas.paulsson at ericsson.com>> wrote: >> >> I looked at SplitKit, but I a...
2017 May 31
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Cool test :) It seems to work fine now, I don't see any new failures. IIUC, Kristof is also giving it another run. Cheers, Diana On 30 May 2017 at 22:57, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > I’ve actually gone ahead and pushed the fix as I was able to produce a > small reproducer. > > This is r304244 > > Let me know if you encounter any other problem. > > Cheers, > -Quentin > > On May...
2017 May 29
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Thanks Quentin, it's in progress now, I'll let you know how it goes. Cheers, Diana On 27 May 2017 at 03:36, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Kristof, > > I’ve pushed the localizer in r304051 and added it in the AArch64 O0 pipeline > in r304052. > > I let Dian...
2014 Sep 05
5
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
...little "overkill" to me. In this case you could just simply transfer the value of the kill flag from the SrcReg to the DstReg. We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg. Therefore, I still think, this is the right fix. -Quentin > > -Juergen > > On 09/05/14, Quentin Colombet <qcolombet at apple.com> wrote: >> >> Hi Patrik, >> >> >> LGTM. >> >> Thanks, >> -Quentin >> On Sep 5, 2014, at 1:03 AM, Patrik Hägglund H <patrik.h.hagglund at e...
2015 May 27
6
[LLVMdev] [Shrink-Wrapping] Request For Benchmarking: X86 and AArch64
...ecedence over whatever is set for EnableShrinkWrap. Please report any problem specific to this optimization turned on. A PR with a small IR to reproduce are appreciated. Note: I’ve seem up to 4% runtime improvements on the LLVM test-suite + specs for Os and O3. Thanks in advance for your help, -Quentin
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not personally do the 3.4 to 3.6 por...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the SimpleValueT...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...egs:%vreg1 RetRA This is what I get. This is what I'd like to get: BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; PTRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg0 RetRA On Tue, Aug 25, 2015 at 3:56 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Oh, could you paste the MIs you get right after ISel (the whole def use > chain of the interesting vregs)? > > Q. > > On Aug 25, 2015, at 12:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > AddRegisterOperand calls...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...it gets constrained even more. Honestly, I really don't understand this part at all, why even have this type checking? If we have defined a RegClass for that instruction, it should use that regclass or subregclasses (depending on use/def info), correct? On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the > multiclass. The IMM in my case is a global. So you can see that > GPRBaseRegs,...
2017 May 19
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
On 18 May 2017 at 19:09, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > >> On May 18, 2017, at 1:15 AM, Diana Picus <diana.picus at linaro.org> wrote: >> >> On 18 May 2017 at 09:06, Kristof Beyls <Kristof.Beyls at arm.com> wrote: >>> I think Diana found that when e...
2017 May 22
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin, I actually did a run with -mllvm -optimize-regalloc -mllvm -regalloc=greedy over the weekend and the test does pass with that. Haven't measured the compile time though. Cheers, Diana On 19 May 2017 at 19:06, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > On...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...is perfectly allowed for the MOV16Copy instruction. I really just want to know if there is any way currently to get the TD defined register class for an operand for a machine instruction. There must be a way since LLVM produces valid registers for the operands. On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > Re...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(directStore (dstType (OpNode (srcAType (load addr16:$srcA)))), addr16:$dstD)]>; } defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, i16, i16, simm16, immSExt16x>; On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > 1. I'll take a look, it's also picking the reg class by the > SimpleValueType and then getting the common subclass. Choosing to constrain > the reg class to GPRRegs instead of GPRBaseRegs seems like it could lead to > unintended spilling? If GPRBaseRegs was used then y...
2015 Jul 31
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Quentin, It's in the instruction selection, sorry I forgot to mention that. The Vreg class is GPR and an extra COPY is generated to copy from the GPR to the Base Reg, even though my 'mov' instruction has Base in the Register class list. On Fri, Jul 31, 2015 at 12:50 PM, Quentin Colombet &lt...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Quentin, This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in f...
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin, Am 01.11.2014 um 00:39 schrieb Quentin Colombet <qcolombet at apple.com>: > > On Oct 31, 2014, at 11:00 AM, Boris Boesler <baembel at gmx.de> wrote: > >> Hi Quentin, >> >> I added some debug output (N->dump()) in ::Select(SDNode*N) and compared it to...
2017 May 18
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
On 18 May 2017 at 09:06, Kristof Beyls <Kristof.Beyls at arm.com> wrote: > I think Diana found that when enabling r299283, the bootstrap failed with > llvm-tblgen segfaulting. > So there clearly is some work required there. Indeed. @Quentin, what is the status of that patch? Have you been working on it since then? Should I investigate the segfault more and send you a reproducer? Is this patch the way forward, or do you have other ideas for reducing the stack usage? Thanks, Diana > > Thanks, > > Kristof > > > On...