search for: alu32

Hi, Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. Instructions are defined as follow in TableGen: defm ADD64 : ALU32<"add", 1, 1, addc>; defm ADD64C : ALU32<"addrc", 1, 2, adde>; Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. Is there a default guarantee that nothing will ever be in...

On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > Hi, > > Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. > > Instructions are defined as follow in TableGen: > defm ADD64 : ALU32<"add", 1, 1, addc>; > defm ADD64C : ALU32<"addrc", 1, 2, adde>; > > > Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. > Is there a default guarantee tha...

...> > On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > > Hi, > > Let's say we have a 32-bit architecture where 64-bit additions are done > using 2 operations. > > Instructions are defined as follow in TableGen: > defm ADD64 : ALU32<"add", 1, 1, addc>; > defm ADD64C : ALU32<"addrc", 1, 2, adde>; > > > Let's assume that the carry bit is implicit and that the 2 operations must > *always* be stuck together for the 64-bit add to work properly. > Is there a default guarantee...

...g for. -Quentin On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > Hi, > > Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. > > Instructions are defined as follow in TableGen: > defm ADD64 : ALU32<"add", 1, 1, addc>; > defm ADD64C : ALU32<"addrc", 1, 2, adde>; > > > Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. > Is there a default guarantee tha...

..., 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > >> Hi, >> >> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. >> >> Instructions are defined as follow in TableGen: >> defm ADD64 : ALU32<"add", 1, 1, addc>; >> defm ADD64C : ALU32<"addrc", 1, 2, adde>; >> >> >> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. >> Is there a de...

...2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > >> Hi, >> >> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. >> >> Instructions are defined as follow in TableGen: >> defm ADD64 : ALU32<"add", 1, 1, addc>; >> defm ADD64C : ALU32<"addrc", 1, 2, adde>; >> >> >> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly. >> Is there a d...

...llvm-project * branch master -> FETCH_HEAD Nothing to push -bash-4.4$ I have the commit to be pushed in my local branch as below: -bash-4.4$ git log --pretty=oneline 6fdc593fc973365dcd5cf4a582d97c0ae44900f6 (HEAD -> bug1) [BPF] fix a CO-RE issue with -mattr=+alu32 3c7c3717932aba864c23edd2e48f1b28a6d532d5 (origin/master, origin/HEAD, master) [CVP] add test for poison propagation bug (PR43802); NFC 2724d9e12960cc1d93eeabbfc9aa1bffffa041cc build: remove `LLVM_CXX_STD` extension point The `git llvm push` used to work for me. Not it stopped working. Does an...

...*** Must match HexagonBaseInfo.h *** >> //===----------------------------------------------------------------------===// >> >> +class Type<bits<5> t> { >> + bits<5> Value = t; >> +} >> +def TypePSEUDO : Type<0>; >> +def TypeALU32 : Type<1>; >> +def TypeCR : Type<2>; >> +def TypeJR : Type<3>; >> +def TypeJ : Type<4>; >> +def TypeLD : Type<5>; >> +def TypeST : Type<6>; >> +def TypeSYSTEM : Type<7>; >> +def TypeXTYPE : Ty...