Displaying 6 results from an estimated 6 matches for "addrc".
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2013 Apr 15
4
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
Hi,
Let's say we have a 32-bit architecture where 64-bit additions are done
using 2 operations.
Instructions are defined as follow in TableGen:
defm ADD64 : ALU32<"add", 1, 1, addc>;
defm ADD64C : ALU32<"addrc", 1, 2, adde>;
Let's assume that the carry bit is implicit and that the 2 operations must
*always* be stuck together for the 64-bit add to work properly.
Is there a default guarantee that nothing will ever be inserted between
"add" and "addrc" or is there a flag/co...
2013 Apr 15
0
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
...t gmail.com> wrote:
> Hi,
>
> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
>
> Instructions are defined as follow in TableGen:
> defm ADD64 : ALU32<"add", 1, 1, addc>;
> defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>
>
> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between "add" and "addrc" o...
2013 Apr 15
2
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
....com> wrote:
>
> Hi,
>
> Let's say we have a 32-bit architecture where 64-bit additions are done
> using 2 operations.
>
> Instructions are defined as follow in TableGen:
> defm ADD64 : ALU32<"add", 1, 1, addc>;
> defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>
>
> Let's assume that the carry bit is implicit and that the 2 operations must
> *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between
> "add" and "addrc...
2013 Apr 15
0
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
...t gmail.com> wrote:
> Hi,
>
> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
>
> Instructions are defined as follow in TableGen:
> defm ADD64 : ALU32<"add", 1, 1, addc>;
> defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>
>
> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
> Is there a default guarantee that nothing will ever be inserted between "add" and "addrc" o...
2013 Apr 16
1
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
...> Hi,
>>
>> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
>>
>> Instructions are defined as follow in TableGen:
>> defm ADD64 : ALU32<"add", 1, 1, addc>;
>> defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>>
>>
>> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
>> Is there a default guarantee that nothing will ever be inserted between "add" and "...
2013 Apr 15
0
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
...> Hi,
>>
>> Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
>>
>> Instructions are defined as follow in TableGen:
>> defm ADD64 : ALU32<"add", 1, 1, addc>;
>> defm ADD64C : ALU32<"addrc", 1, 2, adde>;
>>
>>
>> Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to work properly.
>> Is there a default guarantee that nothing will ever be inserted between "add" and &qu...