llvm dev - Aug 2012 - [LLVMdev] Pseudo instructions expansion

Hi all,
I'm trying to solve a problem that we have in implementation of the
assembler for Mips platform in llvm. Mips has some pseudo instructions that,
depending on the arguments can be emitted as one or more real instructions by
the assembler.

For example load immediate instruction can have multiple expansions depending on
a size of immediate operand:
This expansion is for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
This one is for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
This one is for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)

I have found that class PseudoLoweringEmitter emits code which deals with
PseudoInstExpansion. This sounds like exactly what we need , but, as stated in
comment in PseudoLoweringEmitter.cpp:
// FIXME: This pass currently can only expand a pseudo to a single instruction.
// The pseudo expansion really should take a list of dags, not just
// a single dag, so we can do fancier things.

Are the 'fancier things' mentioned in the comment things that we need,
expansion to a multiple instructions and could they use operand values as
conditions for different expansions?
Could it work for inline asm in C code, with/without direct-object emitter?

Kind Regards

Vladimir
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Hi Vladimir,

The pass you refer to isn't used by the assembler at all. That's
strictly a compiler codegen thing. The assembler equivalents are expressed via
InstAlias constructions. Again, though, those are for a single output
instruction, so you need something more. Sprecifically, you can handle assembly
pseudo-instructions in C++ code. Something like the ARM assembler's
processInstruction() hook would be an appropriate place.

-Jim


On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at
mips.com> wrote:
> Hi all,
> I'm trying to solve a problem that we have in implementation of the
assembler for Mips platform in llvm. Mips has some pseudo instructions that,
depending on the arguments can be emitted as one or more real instructions by
the assembler.
> For example load immediate instruction can have multiple expansions
depending on a size of immediate operand:
> This expansion is for 0 ≤ j ≤ 65535.
> li d,j =>
> ori d,$zero,j
> This one is for −32768 ≤ j < 0.
> li d,j =>
> addiu d,$zero,j
> This one is for any other value of j that is representable as a 32-bit
integer.
> li d,j =>
> lui d,hi16(j)
> ori d,d,lo16(j)
> I have found that class PseudoLoweringEmitter emits code which deals with
PseudoInstExpansion. This sounds like exactly what we need , but, as stated in
comment in PseudoLoweringEmitter.cpp:
> // FIXME: This pass currently can only expand a pseudo to a single
instruction.
> // The pseudo expansion really should take a list of dags, not just 
> // a single dag, so we can do fancier things. 
> 
> Are the 'fancier things' mentioned in the comment things that we
need, expansion to a multiple instructions and could they use operand values as
conditions for different expansions?
> Could it work for inline asm in C code, with/without direct-object emitter?
> 
> Kind Regards
> 
> Vladimir
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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Hi Jim,
thank you for the quick response. I have used InstAlias in some cases, but these
are really simple pseudo instructions where the  pseudo instruction is more like
a special case of existing one, like using fixed operand or simply a more human
understandable way of presenting an operation. I know that there are predicates
available to improve matching, but can InstAlias use conditions to choose
between different replacements, like the ones I stated for load immediate? I
have thought of expanding instructions after successful match but I was hoping
that there is some kind of mechanism from tableGen that can be used for the
purpose as the former way seems to me more like a hack.

Kind regards

Vladimir
________________________________
From: Jim Grosbach [grosbach at apple.com]
Sent: Thursday, August 09, 2012 6:18 PM
To: Medic, Vladimir
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Pseudo instructions expansion

Hi Vladimir,

The pass you refer to isn't used by the assembler at all. That's
strictly a compiler codegen thing. The assembler equivalents are expressed via
InstAlias constructions. Again, though, those are for a single output
instruction, so you need something more. Sprecifically, you can handle assembly
pseudo-instructions in C++ code. Something like the ARM assembler's
processInstruction() hook would be an appropriate place.

-Jim


On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at
mips.com<mailto:vmedic at mips.com>> wrote:

Hi all,
I'm trying to solve a problem that we have in implementation of the
assembler for Mips platform in llvm. Mips has some pseudo instructions that,
depending on the arguments can be emitted as one or more real instructions by
the assembler.

For example load immediate instruction can have multiple expansions depending on
a size of immediate operand:
This expansion is for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
This one is for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
This one is for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)

I have found that class PseudoLoweringEmitter emits code which deals with
PseudoInstExpansion. This sounds like exactly what we need , but, as stated in
comment in PseudoLoweringEmitter.cpp:
// FIXME: This pass currently can only expand a pseudo to a single instruction.
// The pseudo expansion really should take a list of dags, not just
// a single dag, so we can do fancier things.

Are the 'fancier things' mentioned in the comment things that we need,
expansion to a multiple instructions and could they use operand values as
conditions for different expansions?
Could it work for inline asm in C code, with/without direct-object emitter?

Kind Regards

Vladimir
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