search for: instalia

...nstrSystem.td =================================================================== --- lib/Target/X86/X86InstrSystem.td (revision 161828) +++ lib/Target/X86/X86InstrSystem.td (working copy) @@ -445,6 +445,7 @@ def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7; def : InstAlias<"xstorerng", (XSTORE)>; +def : InstAlias<"xstore-rng", (XSTORE)>; let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7; @@ -454,6 +455,12 @@ def XCRYPTOFB : I<0xe8, Ra...

Hello, InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: if (!Hack) PrintFatalError(TheDef->getLoc(), "ERROR: matchable with tied operand '&quot...

Hi, On Instructions you can use checkEarlyTargetMatchPredicate() to check that the operands are the same. There's an example of that in MipsAsmParser.cpp for DATI and DAHI. I can't think of a reason TableGen couldn't be made to allow this for InstAlias too. > On 15 Dec 2017, at 02:12, via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello, > > InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. > > It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp:...

...InstrInfo.td | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td > index f33ae2a..4950674 100644 > --- a/lib/Target/X86/X86InstrInfo.td > +++ b/lib/Target/X86/X86InstrInfo.td > @@ -1971,6 +1971,10 @@ def : InstAlias<"aam", (AAM8i8 10)>; > // Disambiguate the mem/imm form of bt-without-a-suffix as btl. > def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; > > +// Disambiguate btr and bts, just like GNU as. > +def : InstAlias<"btr $imm...

Hi Daniel, I defined checkEarlyTargetMatchPredicate() to explicitly check for the tied operands, and it worked. I could define an alias like: InstAlias<"oldOP $rd, $rd, $rs1", (NEWOP $rd, $rs1)> However, I had to additionally change AsmMatcherEmitter 'Hack' variable setting to allow the repeated operand $rd in the AsmString. Do you or anyone else know the history with this 'Hack' flag? Thanks, Ana. diff --git...

On Jan 16, 2013, at 10:07 AM, Brad Smith <brad at comstyle.com> wrote: > I was wondering if someone with more familiarity with MC > on X86 could consider looking into adding support for > the hyphenated versions of the VIA Padlock instructions? Take a look at llvm/lib/Target/X86InstrSystem.td perhaps. -- Stephen Checkoway

I was wondering if someone with more familiarity with MC on X86 could consider looking into adding support for the hyphenated versions of the VIA Padlock instructions? If anyone is up for it there are details within these two bug reports.. http://www.llvm.org/bugs/show_bug.cgi?id=8556 http://www.llvm.org/bugs/show_bug.cgi?id=10266 -- This message has been scanned for viruses and dangerous

...t; 1 file changed, 4 insertions(+) >> >> diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td >> index f33ae2a..4950674 100644 >> --- a/lib/Target/X86/X86InstrInfo.td >> +++ b/lib/Target/X86/X86InstrInfo.td >> @@ -1971,6 +1971,10 @@ def : InstAlias<"aam", (AAM8i8 10)>; >> // Disambiguate the mem/imm form of bt-without-a-suffix as btl. >> def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; >> >> +// Disambiguate btr and bts, just like GNU as. >> +def : InstAlia...

Hi Jim, thank you for the quick response. I have used InstAlias in some cases, but these are really simple pseudo instructions where the pseudo instruction is more like a special case of existing one, like using fixed operand or simply a more human understandable way of presenting an operation. I know that there are predicates available to improve matching, b...

Hi Vladimir, The pass you refer to isn't used by the assembler at all. That's strictly a compiler codegen thing. The assembler equivalents are expressed via InstAlias constructions. Again, though, those are for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's processInstruction() hook would be an appropriate place. -Jim On Aug 9, 2012, at 3:...

Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the assembler. For example load immediate instruction can have multiple expansions depending on a size of immediate operand: This expansion is for 0 ≤ j ≤ 65535. li

...;m working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have s...

On Wednesday 10 July 2013 22:18:23 Jevin Sweval wrote: > http://www.cs.fsu.edu/~baker/devices/lxr/http/source/linux/arch/x86/include/ > asm/bitops.h#L68 > > Here is one example that I found. Are the inline assembly arguments > ambiguous in size? It would help us for sure to build the kernel and others. -- JS

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

...;m working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have s...

...> > I've had a look at Mips(64)InstrInfo.td which seems to be where the > syntax is defined, but since this is my first encounter with > clang/llvm's internals, I'm not sure how to go about making the change. > Could someone give me some pointers? Is this something that InstAlias > can handle? > > An alternative workaround would be to just use gas as-is, but it gets > upset by the .cfi_section directives that clang emits. Is there some > way to suppress those (while keeping the rest of the cfi directives that > this version of gas does understand)? >...

...;m working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have s...

...tPrintAliasInstruction seems to ignore instruction aliases if an operand that is not a register nor an immediate appears in the result instruction DAG. For example, the folllowing instruction alias pattern is not handled in MipsGenAsmWriter.inc because the third operand of BEQ is a brtarget: def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset)>; The code which decides not to include this alias is located near line 856 in AsmWriterEmitter.cpp: for (unsigned i = 0, e = LastOpNo; i != e; ++i) { ... switch (RO.Kind) { case CodeGenInstAlias::ResultOperand::K_Record: { .....

...egrated-as is enabled). I've had a look at Mips(64)InstrInfo.td which seems to be where the syntax is defined, but since this is my first encounter with clang/llvm's internals, I'm not sure how to go about making the change. Could someone give me some pointers? Is this something that InstAlias can handle? An alternative workaround would be to just use gas as-is, but it gets upset by the .cfi_section directives that clang emits. Is there some way to suppress those (while keeping the rest of the cfi directives that this version of gas does understand)? Thanks, J

I'm having trouble getting TableGen to generate disassembler code. The issue is that I have several TableGen definitions that emit the same instruction encoding. This results in TableGen complaining about encoding conflicts (and not handling those instructions). For example, general purpose registers in the architecture I'm targeting can hold floating point or integer values. As such, I