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...re for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's processInstruction() hook would be an appropriate place. -Jim On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at mips.com<mailto:vmedic at mips.com>> wrote: Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the ass...

...re for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's processInstruction() hook would be an appropriate place. -Jim On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > Hi all, > I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the assembler. > For examp...

Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the assembler. For example load immediate instruction can have multiple expansions depending on a size of immediate operand: This expansion is for 0 ≤ j ≤ 65535. li

On May 22, 2012, at 8:05 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. > In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination registe...

I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. For example ceil.w.s means both source and destination are F32 registers while ceil.l.d means both source and destination are F64

...ider,papin_g,pcc,predmond,rafael,rdivacky,redstar,rengolin,resistor,revane,ributzka,rikka,rkotler,rlytton,rmitton,rnk,row,rsandifo,rsmith,rtrieu,rudkx,ruiu,samsonov,sbaranga,sbenza,sdt,sepavloff,shuxin_yang,silvas,stephenwlin,stoklund,sylvestre,tasiraj,timurrrr,tnorthover,tstellar,uweigand,venkatra,vmedic,void,whunt,wpan,wschmidt,ygao,yjiang > > BUILD FAILED: failed compile > > sincerely, > -The Buildbot > > >

I'm trying to build a standalone assembler for Mips using AsmParser and I'm facing a problem with assembly directives. Mips assembler has following syntax for .set directive .set reorder or .set noreorder which allow/disallow assembler to change the order of instructions in the block that follows. As the implemented AsmParser requires .set directive to have the following syntax: