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2008 Jun 11
0
[LLVMdev] Possible miscompilation?
On 2008-06-11, at 13:16, Gary Benson wrote:
> Duncan Sands wrote:
>
>> Can you please attach IR which can be compiled to an executable
>> (and shows the problem).
>
> I've been generating functions using a builder and then compiling
> them with ExecutionEngine::getPointerToFunction(). Is there some way
> I can get compilable IR from that?
2008 Jun 11
2
[LLVMdev] Possible miscompilation?
Duncan Sands wrote:
> Can you please attach IR which can be compiled
> to an executable (and shows the problem).
I've been generating functions using a builder and then
compiling them with ExecutionEngine::getPointerToFunction().
Is there some way I can get compilable IR from that?
Cheers,
Gary
--
http://gbenson.net/
2007 Apr 03
2
[LLVMdev] Live intervals and aliasing registers problem
..., i32 %b) {
>> entry:
>> %retval = select i1 false, i32 %a, i32 %b ;
>> <i32> [#uses=0]
>> ret void
>> }
>>
>> I get this error:
>>
>> entry (0x8503b90, LLVM BB @0x8501b00, ID#0):
>> %reg1024 = ORI %R0, 0
>> %reg1025 = ORI %R1, 0
>> RETL
>> Machine Function
>> ********** REWRITING TWO-ADDR INSTRS **********
>> ********** Function: _Z3fooff
>>
>> ********** COMPUTING LIVE INTERVALS **********
>> ********** Function: _Z3fooii
>&...
2012 May 02
4
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
...the stack pointer.
The second wart is the dead copy to r31...which leads to the
unnecessary save and restore of r31.
For tomcatv, we have to basically save/restore the entire set
of non-volatile integer and fp registers. Looking at how
llvm does that shows:
...
lis 3, 56
ori 3, 3, 57680
stwx 16, 31, 3
lis 3, 56
ori 3, 3, 57684
stwx 17, 31, 3
lis 3, 56
ori 3, 3, 57688
stwx 18, 31, 3
lis 3, 56
ori 3, 3, 57692
stwx 19, 31, 3
lis 3, 56
ori 3, 3, 57696
stwx 20, 31, 3...
2010 Oct 04
2
[LLVMdev] missing blocks
...function
main: # @main
# BB#0: # %entry
addi %r1, %r1, -32
st %r31, %r1,28
st %r12, %r1,24
addi %r12, %r0, 0
st %r12, %r1,20
addi %r2, %r0, 1
call special_format
oris r0,r0,0
subc r0, %r2, %r12
beq .LBB0_2
oris r0,r0,0
b .LBB0_1
oris r0,r0,0
# BB#1: # %if.then
call abort
oris r0,r0,0
.LBB0_2: # %if.end
addi %r12, %r0, 0...
2007 Apr 04
0
[LLVMdev] Live intervals and aliasing registers problem
On Apr 3, 2007, at 3:45 PM, Christopher Lamb wrote:
>
>> Can you dump out the machine basic block? It should have an
>> implicit use of V4R0 at first ORI but it should not be marked kill.
>> If it is marked kill, then you need to walk LiveVariables.cpp to
>> find out why.
>
> Here is the beginning of the BB dump.
>
> entry (0x8503c80, LLVM BB @0x8501af0, ID#0):
> Live Ins: %R0 %R1
> %reg1024 = ORI %R0<kill>, 0
&g...
2012 Apr 29
1
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...32*), align 8
>> %29 = icmp slt i32 %28, 0
>> br i1 %29, label %27, label %loop.exit
>>
>> loop.exit: ; preds = %27
>>
>> llc will generate following MIPS code,
>>
>> $BB0_1:
>> lui $3, 32800
>> ori $3, $3, 1032
>> lw $3, 0($3)
>> bltz $3, $BB0_1
>> nop
>> # BB#2:
>>
>>
>> The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a...
2012 Apr 25
3
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...; preds = %27, %entry
%28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8
%29 = icmp slt i32 %28, 0
br i1 %29, label %27, label %loop.exit
loop.exit: ; preds = %27
llc will generate following MIPS code,
$BB0_1:
lui $3, 32800
ori $3, $3, 1032
lw $3, 0($3)
bltz $3, $BB0_1
nop
# BB#2:
The two operation lui and ori which are used to calculate memory address
actually are loop invariants. They supposed to be moved out of the loop. I
thought it might be a limitation of the MIPS backend. Then I tried the ARM
backend,...
2011 Jan 19
0
[LLVMdev] About test suits Cont2
...11) grep EMITIR *
Here, I get no results. It seems LLVMCC_EMITIR_FLAG was not set during my
configuration.
My linux is Fedora Core 13, cpu is intel i3, and host gcc is 4.4.5.
*
2. After the reconfigure process, I have search LLVM in config.log, and all
the results are below:
[qali at qali llvm-2.8-ori]$ grep "^LLVM" config.log
LLVMCC1='/home/qali/build/llvm-gcc4.2-2.8-x86_64-linux/bin/../libexec/gcc/x86_64-unknown-linux-gnu/4.2.1/cc1'
LLVMCC1PLUS='/home/qali/build/llvm-gcc4.2-2.8-x86_64-linux/bin/../libexec/gcc/x86_64-unknown-linux-gnu/4.2.1/cc1plus'
LLVMCC_OPTION='...
2004 Aug 06
2
OGG123 frozen under certain circumstances while listening at icecast
...0x4001c235 in ov_read () from /usr/radio//lib/libvorbisfile.so.3
#10 0x0804f329 in ovf_read (decoder=0x8079658, ptr=0x80551a0, nbytes=1280, eos=0xbffffc04, audio_fmt=0xbffffc10)
at oggvorbis_format.c:139
#11 0x0804ed48 in play (source_string=0x8055b60 "http://localhost:443/radio-bro-gwened-ori.ogg") at ogg123.c:529
#12 0x0804e9b3 in main (argc=9, argv=0xbffffd74) at ogg123.c:393
<p>and this morning, it was stuck here:
#0 0x401f55d4 in __pthread_sigsuspend () from /lib/libpthread.so.0
#1 0xbf7ff6e0 in ?? ()
#2 0x401f5398 in __pthread_wait_for_restart_signal () from /lib/lib...
2007 Mar 27
0
[LLVMdev] Live intervals and aliasing registers problem
...:
>
> define void @_Z3fooii(i32 %a, i32 %b) {
> entry:
> %retval = select i1 false, i32 %a, i32 %b ;
> <i32> [#uses=0]
> ret void
> }
>
> I get this error:
>
> entry (0x8503b90, LLVM BB @0x8501b00, ID#0):
> %reg1024 = ORI %R0, 0
> %reg1025 = ORI %R1, 0
> RETL
> Machine Function
> ********** REWRITING TWO-ADDR INSTRS **********
> ********** Function: _Z3fooff
>
> ********** COMPUTING LIVE INTERVALS **********
> ********** Function: _Z3fooii
> entry:
> live...
2007 Mar 25
2
[LLVMdev] Live intervals and aliasing registers problem
...R0]>, DwarfRegNum<1>;
when trying to compile:
define void @_Z3fooii(i32 %a, i32 %b) {
entry:
%retval = select i1 false, i32 %a, i32 %b ;
<i32> [#uses=0]
ret void
}
I get this error:
entry (0x8503b90, LLVM BB @0x8501b00, ID#0):
%reg1024 = ORI %R0, 0
%reg1025 = ORI %R1, 0
RETL
Machine Function
********** REWRITING TWO-ADDR INSTRS **********
********** Function: _Z3fooff
********** COMPUTING LIVE INTERVALS **********
********** Function: _Z3fooii
entry:
livein register: R0 killed +[0,2:0)...
2008 Jun 12
4
[LLVMdev] Possible miscompilation?
...2647: mr 4, 13
2648: bl trace_bytecode
2649: lis 13, dump57 at ha
2650: la 3, dump56 at l(14)
2651: mr 4, 26
2652: bl print_value
2653: la 3, dump57 at l(13)
2654: mr 4, 27
2655: bl print_value
2656: ori 4, 21, 7712
2657: li 3, 634
2658: bl trace_bytecode
2659: lis 3, 4031
2660: lwz 3, -12952(3)
2661: cmplwi 0, 3, 1
2662: beq 0, BB10_218 # do_safepoint
2663: BB10_41: # safepointed
2664: cmpw 0, 27, 26
2665: bge...
2020 Apr 18
2
Debug symbols are missing in elf
...;);
return 0;
}
hello.o objdump:
int main()
{
0: 10a00000 addk r5, r0, r0
4: f8a1002c swi r5, r1, 44
printf("Hello World\n\r");
8: b0000000 imm 0
8: R_MICROBLAZE_64 .rodata.str1.1
c: a0c00000 ori r6, r0, 0
10: f8a10028 swi r5, r1, 40
14: b0000000 imm 0
14: R_MICROBLAZE_64_PCREL printf
18: b9f40000 brlid r15, 0
1c: 10a60000 addk r5, r6, r0
printf("Successfully ran Hello World application"...
2012 Apr 29
0
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...81832 to i32*), align 8
> %29 = icmp slt i32 %28, 0
> br i1 %29, label %27, label %loop.exit
>
> loop.exit: ; preds = %27
>
> llc will generate following MIPS code,
>
> $BB0_1:
> lui $3, 32800
> ori $3, $3, 1032
> lw $3, 0($3)
> bltz $3, $BB0_1
> nop
> # BB#2:
>
>
> The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backen...
2016 Oct 18
2
A use of RDF to extend register Remat
...s, RDF would help with that, even if these instructions were not in the
> same block.
>
> Once you have the node corresponding to the use of R3 in the last
> statement, you can get the node corresponding to the reaching def of that
> node. This def node would be a member of the "oris" statement. Within that
> statement you would then look for use nodes and you'd find the use node for
> R3: "oris r3, *r3*, 35809". From that node, you'd follow the reaching def
> and this would give you: "sldi *r3*, r3, 32". Then you'd look for use no...
2012 May 02
0
[LLVMdev] [cfe-dev] Odd PPC inline asm constraint
On Tue, 2012-05-01 at 17:47 -0500, Hal Finkel wrote:
> By default it should build for
> whatever the current host is (no special flags required). To
> specifically build for something else, use:
> -ccc-host-triple powerpc64-unknown-linux-gnu
> or
> -ccc-host-triple powerpc-unknown-linux-gnu
So LLVM isn't biarch capable? Meaning one LLVM compiler cannot
generate both
2008 Sep 23
0
[LLVMdev] Multi-Instruction Patterns
...eene wrote:
> Are there any examples of using tablegen to generate multiple machine
> instructions from a single pattern? Or do these cases always have
> to be
> manually expanded?
PPC has a bunch of examples, for example:
// Arbitrary immediate support. Implement in terms of LIS/ORI.
def : Pat<(i32 imm:$imm),
(ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
// ADD an arbitrary immediate.
def : Pat<(add GPRC:$in, imm:$imm),
(ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
// OR an arbitrary immediate.
def : Pat<(or GPRC:$in, imm:$i...
2016 Sep 12
6
[RFC] Register Rematerialization (remat) Extension
...mple example that currently remat
does
not cover
$ cat ~/tmp/tl.c
void foo(long);
void bar() {
for (int i = 0; i < 1600; ++i)
foo(3494348345984503943);
}
$ clang -O3 -S -o - ~/tmp/tl.c -target powerpc64
...
# BB#0: # %entry
...
lis 3, 12414
ori 3, 3, 27470
sldi 3, 3, 32
oris 3, 3, 35809
ori 30, 3, 20615
...
.LBB0_1: # %for.body
mr 3, 30
bl foo
...
There is a sequence of instructions used to materialize the constant, the
first
one (the lis) is trivially rematerialiable...
2011 Jan 19
0
[LLVMdev] Fwd: About test suits Cont1
...11) grep EMITIR *
Here, I get no results. It seems LLVMCC_EMITIR_FLAG was not set during my
configuration.
My linux is Fedora Core 13, cpu is intel i3, and host gcc is 4.4.5.
*
2. After the reconfigure process, I have search LLVM in config.log, and all
the results are below:
[qali at qali llvm-2.8-ori]$ grep "^LLVM" config.log
LLVMCC1='/home/qali/build/llvm-gcc4.2-2.8-x86_64-linux/bin/../libexec/gcc/x86_64-unknown-linux-gnu/4.2.1/cc1'
LLVMCC1PLUS='/home/qali/build/llvm-gcc4.2-2.8-x86_64-linux/bin/../libexec/gcc/x86_64-unknown-linux-gnu/4.2.1/cc1plus'
LLVMCC_OPTION='...