search for: fancier

If so, please run the following: ftp://ftp.kernel.org/pub/linux/utils/boot/syslinux/Testing/vesatest/ (either the floppy image or the iso CD-ROM image is fine. Both are images that should be booted.) This will help me collect information about video cards. I'll need you to email me the type of video card, the output of this program, and what happens when this program "tests"

...with PseudoInstExpansion. This sounds like exactly what we need , but, as stated in comment in PseudoLoweringEmitter.cpp: // FIXME: This pass currently can only expand a pseudo to a single instruction. // The pseudo expansion really should take a list of dags, not just // a single dag, so we can do fancier things. Are the 'fancier things' mentioned in the comment things that we need, expansion to a multiple instructions and could they use operand values as conditions for different expansions? Could it work for inline asm in C code, with/without direct-object emitter? Kind Regards Vladimir...

Hi thank you for talking the time to help me with this. I have a sequence of numbers in a file and an equal sequence of various character, say(a b c d) each occurs more than once. I need to plot the numbers so that numbers corresponding to a in the other sequence would have green dots, those corresponding to b a red dot, nothing on c and blue square for d. i.e 2 a show a green dot 4 b show a

...ansion. This sounds like exactly what we need , but, as stated in comment in PseudoLoweringEmitter.cpp: > // FIXME: This pass currently can only expand a pseudo to a single instruction. > // The pseudo expansion really should take a list of dags, not just > // a single dag, so we can do fancier things. > > Are the 'fancier things' mentioned in the comment things that we need, expansion to a multiple instructions and could they use operand values as conditions for different expansions? > Could it work for inline asm in C code, with/without direct-object emitter? > &g...

...is responsible for lowering pseudo-instructions to real machine instructions. In the code is this comment: // FIXME: This pass currently can only expand a pseudo to a single instruction. // The pseudo expansion really should take a list of dags, not just // a single dag, so we can do fancier things. Does anyone think that enhancing it to expand to multiple instructions is worth the effort?

...us some random tweak. In python, I would write: vec = [100] * 50 # make a 50-element list with each element set to 100 from random import randint for i, v in enumerate(vec): if i is not 0: # if we're not on the first element vec[i] = vec[i-1] + randint(-2, 2) I suspect R has some fancier way of doing this. How to? TIA -- A better way of running series of SAS programs: http://overlook.homelinux.net/wilsonwiki/SasAndMakefiles

On 02/15/2016 04:20 PM, Frank Cox wrote: > On Mon, 15 Feb 2016 14:57:25 -0500 > ken wrote: > >> Is there a way to make the font of some of the text in a zenity-created >> window larger? This property doesn't seem to be configurable in any >> way. If it matters, I'm using text entry (--entry) mode. > >

...her searching on the wrong thing, or have totally the wrong idea... Can anyone suggest if the following is possible? Currently, our office has a 24 analogue extension PBX, and 2 ISDN lines providing it with external connectivity. We have several analogue extensions spare, but no capacity to add fancier connectors to link to an asterisk system (as most of the PBX linking guides detail). All our phones are bog standard analogue ones. We'd like to use an asterisk system to allow some calls to be routed out via a VoIP gateway. We'd also like to allow some inbound SIP calls to be handed to...

...with PseudoInstExpansion. This sounds like exactly what we need , but, as stated in comment in PseudoLoweringEmitter.cpp: // FIXME: This pass currently can only expand a pseudo to a single instruction. // The pseudo expansion really should take a list of dags, not just // a single dag, so we can do fancier things. Are the 'fancier things' mentioned in the comment things that we need, expansion to a multiple instructions and could they use operand values as conditions for different expansions? Could it work for inline asm in C code, with/without direct-object emitter? Kind Regards Vladimir...

...pening while avoiding pessimizing the common case, I'm proposing adding a "halting" function attribute which is a hint to the optimizers that a function is guaranteed to halt. A pretty simple conservative implementation would be as a "contains no loops" analysis. Obviously fancier implementations are possible, but we'd like to avoid having the FunctionAttrs depend on LoopInfo or SCEV which would be needed for loop finiteness analysis. Additionally, we already have the LoopDeletion pass interleaved, which should handle exactly those cases anyways. Thoughts? --Owen

...scan.c /home/src/usr.bin/colldef/parse.y:32: arpa/inet.h: No such file or directory mkdep: compile failed *** Error code 1 I looked in /usr/obj/home/src/i386/usr/include/arpa/ and indeed, inet.h is not there, but I can't figure out why. This is starting with a clean obj directory, and nothing fancier than 'make -DNOCLEAN buildworld'. Doug -- This .signature sanitized for your protection

...uilding an llvm back end :-) I have read the documentation and taken a look on the X86 back end. It looks quiet simple to get a very minimal back end working. I am considering for a first version: 1) only support the 32 bits ABI 2) Ignore the shifter (i.e use only 8 bits immediates) 3) Ignore the fancier addressing modes Without this, the generated code with not be very good but the back end will be very simple. The only part that appears to require more work is describing the instructions set. Am I underestimating how hard it is? How much work do you thing is required to have this minimal back e...

...think anyone tries to do :). > > Yes, global growth limit may be good for size control, but is a hack for control icache footprint. However, as I mentioned, the bottom up inline scheme make it impossible to use any heuristics involving 'global limit' which can be more complicated and fancier than the simple growth limit. For instance, there is no restriction that only one global limit can be used --- the compiler can partition the call graph into multiple locality regions, and set icache limit for each region. The inlining order can be done on a region by region basis. For each regio...

...ode for implementing them. All the globalmodref, scev-aa, steenaa and ds-aa are only subclasses of the AliasAnalysis class, so I cannot see how ds-aa can automatically call basicaa. What I guess is that the order of the flags matters. This means if I want to chain a simple AA (say, -basicaa) and a fancier one (ds-aa), I should add the -basicaa before -ds-aa to define the chain, which the AnalysisGroup can understand. If I add ds-aa before basicaa, does that mean basicaa will chain with ds-aa backward? > > The chaining is used with masking of the results to ensure that the > result only be...

...o :). >> > > Yes, global growth limit may be good for size control, but is a hack for > control icache footprint. However, as I mentioned, the bottom up inline > scheme make it impossible to use any heuristics involving 'global limit' > which can be more complicated and fancier than the simple growth limit. For > instance, there is no restriction that only one global limit can be used --- > the compiler can partition the call graph into multiple locality regions, > and set icache limit for each region. The inlining order can be done on a > region by region b...

...y regularity can probably be counted on one hand. IIRC glibc invokes CPUID to gather TLB/cache info, XCR0-based features, and one or two other leafs. A statically sized global array that's arbitrarily index a la x86_capability would be just as simple and more performant. It would also allow fancier things like emulating CPUID 0xD in the guest if you want to go down that road.

...y regularity can probably be counted on one hand. IIRC glibc invokes CPUID to gather TLB/cache info, XCR0-based features, and one or two other leafs. A statically sized global array that's arbitrarily index a la x86_capability would be just as simple and more performant. It would also allow fancier things like emulating CPUID 0xD in the guest if you want to go down that road.

...think anyone tries to do :). > > Yes, global growth limit may be good for size control, but is a hack for control icache footprint. However, as I mentioned, the bottom up inline scheme make it impossible to use any heuristics involving 'global limit' which can be more complicated and fancier than the simple growth limit. For instance, there is no restriction that only one global limit can be used --- the compiler can partition the call graph into multiple locality regions, and set icache limit for each region. The inlining order can be done on a region by region basis. For each regio...

...it will take less time to implement a YAML-based solution. My concern is that you may run out of time to complete this and the file format is not the most important thing in this project. Getting it to work, if only as a proof of concept, would be very helpful to everyone. Coming up with a fancier grammar and implementing a parser for it could be done later on top of the initial implementation. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

On 07/03/2013 06:18 PM, Chandler Carruth wrote: > > Your understanding is correct -- this is impossible. What are you > really trying to do? > I'm working on implementation of some fancier alias analysis algorithm. I have experienced strange behavior when I registered my AA (as module pass) into AA group. Somehow I was unable to get correct DataLayout from AA interface. So I wanted to try to make it immutable, just like other AA implementations. Anyway, thanks for clarification.