search for: processinstruct

...IntegerType i1. I'm not certain I've found the root cause of the problem yet, it's probably due to my handling of LLVMContext & Module life cycles, and this is my first real look at llvm's source. This patch at least makes my problem go away; @@ -2195,11 +2200,11 @@ bool GVN::processInstruction(Instruction *I) { BasicBlock *Parent = BI->getParent(); bool Changed = false; - Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext()); + Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext()); BasicBlockEdge TrueE(Parent, TrueSucc); Changed |=...

...trictly a compiler codegen thing. The assembler equivalents are expressed via InstAlias constructions. Again, though, those are for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's processInstruction() hook would be an appropriate place. -Jim On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > Hi all, > I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instruction...

...certain I've found the root cause of the problem yet, it's > probably due to my handling of LLVMContext & Module life cycles, and > this is my first real look at llvm's source. > > This patch at least makes my problem go away; > > @@ -2195,11 +2200,11 @@ bool GVN::processInstruction(Instruction *I) { > BasicBlock *Parent = BI->getParent(); > bool Changed = false; > > - Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext()); > + Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext()); > BasicBlockEdge TrueE(Pa...

Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the assembler. For example load immediate instruction can have multiple expansions depending on a size of immediate operand: This expansion is for 0 ≤ j ≤ 65535. li

...trictly a compiler codegen thing. The assembler equivalents are expressed via InstAlias constructions. Again, though, those are for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's processInstruction() hook would be an appropriate place. -Jim On Aug 9, 2012, at 3:26 AM, "Medic, Vladimir" <vmedic at mips.com<mailto:vmedic at mips.com>> wrote: Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has...

...LI=0x000000010a1a20c8) + 101 at GVN.cpp:1706 > frame #8: 0x0000000103408eef libLTO.dylib`(anonymous > namespace)::GVN::processLoad(this=0x000000010e6ce680, L=0x000000010a1a20c8) > + 1551 at GVN.cpp:1905 > frame #9: 0x00000001034080fd libLTO.dylib`(anonymous > namespace)::GVN::processInstruction(this=0x000000010e6ce680, > I=0x000000010a1a20c8) + 397 at GVN.cpp:2220 > frame #10: 0x0000000103407d1b libLTO.dylib`(anonymous > namespace)::GVN::processBlock(this=0x000000010e6ce680, > BB=0x000000010a19ffa0) + 251 at GVN.cpp:2394 > frame #11: 0x0000000103401755 libLTO.dyl...

On Fri, Jul 17, 2015 at 9:13 AM Evgeny Astigeevich < evgeny.astigeevich at arm.com> wrote: > It’s Dhrystone. > Dhrystone has historically not been a good indicator of real-world performance fluctuations, especially at this small of a shift. I'd like to see if we see any fluctuation on larger and more realistic application benchmarks. One advantage of the flag being set is that we