llvm dev - Jul 2012 - [LLVMdev] Instructions working on 64bit registers without true support for 64bit operations

Hi LLVM-Folks,

at our department we have an in-house developed back-end for the
TriCore processor and we want to upgrade it to LLVM 3.1. However, we
have some troubles regarding some instructions that work on 64bit
registers:

The TriCore processor has 16 32bit registers that can be paired to
form 64bit registers. Except a few instructions all work on 32bit
registers, thus the TriCore processor does not truly support 64bit
operations. These exceptional operations are division and
multiplication, for instance. In the tablegen files these registers
and the corresponding register class are modelled accordingly and the
instruction selector also selects them.

The paired 64bit register class is however not added within the
constructor of the TriCoreTargetLowering class. So, at some point
GetCostForDef is called for a MVT::i64 in connection with a division
instruction and this call segfaults as there just is no matching
register class available for TriCore.

Unfortunately, just adding the register class for MVT::i64 does not
help either. In that case the code generation framework assumes that
the TriCore could deal with MVT::i64 values and no longer expands all
the MVT::i64-stuff to MVT::i32-stuff during type legalization. As the
interface to configure the TypeLegalizeActions is not open to the
particular target implementations, I just did a quick and dirty hack
to tell the TypeLegalizer to expand operations on MVT::i64 values.
Though, this triggers an assertion in
"SelectionDAGLegalize::LegalizeOp".

Before I am going to do more "unguided hacking and guessing", I want
to task if there is an "official way" to support the setup described
above, i.e. having instructions working an 64bit registers (composed
of pairs of 32bit registers) without true support for MVT::i64 values.

Ciao, Fabian

Fabian,
 We have a very similar setup with the AMDIL backend(some operations support
64bit some don't).

What we do is we enable MVT::i64, set legal to all operands that are legal and
then set everything else to expand.

Micah
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Fabian Scheler
> Sent: Wednesday, June 13, 2012 4:05 AM
> To: LLVM Developers Mailing List
> Subject: [LLVMdev] Instructions working on 64bit registers without true
> support for 64bit operations
> 
> Hi LLVM-Folks,
> 
> at our department we have an in-house developed back-end for the
> TriCore processor and we want to upgrade it to LLVM 3.1. However, we
> have some troubles regarding some instructions that work on 64bit
> registers:
> 
> The TriCore processor has 16 32bit registers that can be paired to
> form 64bit registers. Except a few instructions all work on 32bit
> registers, thus the TriCore processor does not truly support 64bit
> operations. These exceptional operations are division and
> multiplication, for instance. In the tablegen files these registers
> and the corresponding register class are modelled accordingly and the
> instruction selector also selects them.
> 
> The paired 64bit register class is however not added within the
> constructor of the TriCoreTargetLowering class. So, at some point
> GetCostForDef is called for a MVT::i64 in connection with a division
> instruction and this call segfaults as there just is no matching
> register class available for TriCore.
> 
> Unfortunately, just adding the register class for MVT::i64 does not
> help either. In that case the code generation framework assumes that
> the TriCore could deal with MVT::i64 values and no longer expands all
> the MVT::i64-stuff to MVT::i32-stuff during type legalization. As the
> interface to configure the TypeLegalizeActions is not open to the
> particular target implementations, I just did a quick and dirty hack
> to tell the TypeLegalizer to expand operations on MVT::i64 values.
> Though, this triggers an assertion in
> "SelectionDAGLegalize::LegalizeOp".
> 
> Before I am going to do more "unguided hacking and guessing", I
want
> to task if there is an "official way" to support the setup
described
> above, i.e. having instructions working an 64bit registers (composed
> of pairs of 32bit registers) without true support for MVT::i64 values.
> 
> Ciao, Fabian
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Hi Micah,
>  We have a very similar setup with the AMDIL backend(some operations
support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal
and then set everything else to expand.
thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer term is almost over now and I can get back to this.

I already tried what you suggested, however I still end up getting the
following error message:

LLVM ERROR: Cannot select: 0x2299fb0: i64 = Constant<1> [ORD=1] [ID=1]

Just setting the Action to Expand here via

 setOperationAction(ISD::Constant,MVT::i64,Expand);

does not solve the problem. I took a look into your AMDIL-patch and
found out that your target supports this operation. I have the feeling
that this has to be lowered manually or has to be handled by
ISelDAGtoDAG or similar.

Well, I guess I have to dig a little bit deeper. If you have any other
suggestion - I definitely am interested ;-)

Ciao, Fabian