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Hi, when I run WINWORD.EXE with wine 0.9.7. I get a lot of command line output (see below). The MS WORED seems fine. Is this normal? if not, what is the problem and how to fix it? Yuandan fixme:imm:ImmGetContext (0x20066): stub fixme:imm:ImmSetCandidateWindow (0x7ff5ae50, 0x307b2d5c): stub fixme:imm:ImmReleaseContext (0x20066, 0x7ff5ae50): stub fixme:imm:ImmGetContext (0x20066): stub fixme:imm:ImmReleaseContext (0x20066, 0x7ff5ae50): stub fixme:imm:ImmGetContext (0x20066): stub fixme:imm:ImmS...

..._c/Programme/TOPIX5 Arbeitsplatz 2008$ topix5.e xe could not open file '/etc/apt/sources.list' bash: topix5.exe: command not found egondolf at Kubuntu-eg:~/.wine/drive_c/Programme/TOPIX5 Arbeitsplatz 2008$ wine top ix5.exe fixme:win:WINNLSEnableIME hUnknown1 0x10026 bUnknown2 1: stub! fixme:imm:ImmGetOpenStatus (0x13c9f0): semi-stub fixme:imm:ImmReleaseContext (0x10026, 0x13c9f0): stub fixme:imm:ImmGetOpenStatus (0x13c9f0): semi-stub fixme:imm:ImmGetOpenStatus (0x13c9f0): semi-stub fixme:advapi:LookupAccountNameW L"" L"egondolf" (nil) 0x32e744 (nil) 0x32e74c 0x 32e748...

...o run 4DClient with wine. It's look working with the last developement version and using winetricks to install the riched20 pakage. We run 4D Client by, wine 4DClient.exe and we have this log: Code: fixme:win:WINNLSEnableIME hUnknown1 0x1003a bUnknown2 1: stub! fixme:imm:ImmGetOpenStatus (0x15bca8): semi-stub fixme:imm:ImmReleaseContext (0x1003a, 0x15bca8): stub fixme:imm:ImmGetOpenStatus (0x15bca8): semi-stub fixme:dsalsa:IDsDriverBufferImpl_SetVol...

...LE through wine... I get WINE setup and can run IE6, however when i run the maye.exe installer, the installer launches, hangs, then eventually crashes... Not sure where to really go from here... Any advice or suggestions would be greatly appreciated... wine "c:\temp\maya.exe" fixme:imm:ImmGetContext (0x10020): stub fixme:imm:ImmReleaseContext (0x10020, 0x7fdd5e10): stub fixme:imm:ImmGetContext (0x10026): stub fixme:imm:ImmReleaseContext (0x10026, 0x7fdd5e10): stub fixme:imm:ImmGetContext (0x10028): stub fixme:imm:ImmReleaseContext (0x10028, 0x7fdd5e10): stub fixme:imm:ImmGe...

...OORD[1], PERSPECTIVE DCL IN[3], TEXCOORD[2], PERSPECTIVE DCL IN[4], TEXCOORD[3], PERSPECTIVE DCL IN[5], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL CONST[19] DCL CONST[0..2] DCL CONST[4..13] DCL TEMP[0] DCL TEMP[1..13], LOCAL IMM[0] FLT32 { 0.1250, 2.0000, 0.8000, 0.1000} IMM[1] FLT32 { 7.5000, -0.5000, 0.0000, 1.0000} IMM[2] FLT32 {16384.0000, 4098.0000, -1.0000, 4094.0000} IMM[3] FLT32 { 0.0025, 0.0500, 0.9990, 0.0010} IMM[4] FLT32 { 0.3333, 7.0000, 0.5000, 300...

...and I can start using the following DLL overrides / config: [AppDefaults\\CorelDrw.exe\\Version] "Windows"="nt40" [AppDefaults\\CorelDrw.exe\\WinMM] "Drivers" = "" [AppDefaults\\CorelDrw.exe\\DllOverrides] "wintab32" = "native" "imm,imm32" = "native" which I guessed based on the points where it used to choke when I tried to run it with the defaults. However, when running "wine CorelDrw.exe", I see the interface appear, but several parts are not drawn properly. For example, many of the toolbar icons a...

On Sep 23, 2008, at 11:26 AM, David Greene wrote: > Are there any examples of using tablegen to generate multiple machine > instructions from a single pattern? Or do these cases always have > to be > manually expanded? PPC has a bunch of examples, for example: // Arbitrary immediate support. Implement in terms of LIS/ORI. def : Pat<(i32 imm:$imm), (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; // ADD an arbitrary immediate. def : Pat<(add GPRC:$in, imm:$imm), (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; // OR an arbitrar...

Are there any examples of using tablegen to generate multiple machine instructions from a single pattern? Or do these cases always have to be manually expanded? -Dave

I am looking for a way to define patterns without specifying the type of the root node in the RHS result. I want to be able to write something like this: def : Pat<(i64 imm:$in), (GenDAG imm:$in)>; (GenDAG is a custom function that returns the DAG that replaces the node in the LHS.) A little background: Mips emits a sequence of instructions to load immediate constants that do not fit in the 16-bit immediate field of an instruction. The number or types of instruct...

...alue to access its subregisters. 2. Use a pattern consisting of INSERT_SUBREG-nodes A colleague of mine (who originally implemented the TriCore-backend) suggested to use a pattern that replaces 64bit-constants by tow INSERT_SUBREG-nodes. I ended up having the following pattern: def : Pat<(i64 imm:$imm), (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (i32 (LO32 imm:$imm)), sub_even), (i32 (HI32 imm:$imm)), sub_odd)>; OK, this leaves a DAG where all i64-Constant-nodes are replaced by to nested INSERT_SUBREG-nodes, but how do I get rid of...

...or (0x21c): stub fixme:xinput:XInputGetState (1 0x256fca8) fixme:thread:SetThreadIdealProcessor (0x260): stub fixme:thread:SetThreadIdealProcessor (0x264): stub fixme:imm:ImmGetOpenStatus (0x159eb8): semi-stub fixme:imm:ImmReleaseContext (0x3002a, 0x159eb8): stub fixme:imm:ImmGetOpenStatus (0x159eb8): semi-stub fixme:imm:ImmGetOpenStatus (0x159eb8): semi-stub...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant for my need. Copying imm to reg w...

Hi, yeah in the long run showing both in an ordered manner would be a nice thing to have! That would include patching the output and the tgsi parser (who wants to delete half the output to parse it again e.g. with nouveau_compiler). I can image an output similar to the one below: IMM[5] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} ^ IMM[5] FLT32 {0x00000019, 0x0000000f, 0x00000005, 0x0000001e} IMM[6] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} = IMM[6] FLT32 {0x0000001e, 0x00000005, 0x0000000a, 0x00000014} IMM[7] FLT32 { 0.0000, 0.0000, 0.0000,...

Hi Kevin, To get some portion of a constant immediate you can use SDNodeXForms to transform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO1...

...s and eliminate a lot of tweaky flag setting/checking around opaque constants. It's going well for the IR and x86, but I now I need to sort out details for all the other targets. To start, can someone please advise on the AAarch64 equivalent of these X86 patterns? // Opaque values become mov immediate to register def : Pat<(i64 (opaque imm:$src)), (MOV64ri imm:$src)>; def : Pat<(i32 (opaque imm:$src)), (MOV32ri imm:$src)>; def : Pat<(i16 (opaque imm:$src)), (MOV16ri imm:$src)>; The 'opaque' here is of course hiding the immediate from folding. What I'm looking...

...chine instruction but sometimes if a vector_shuffle can only return LHS or RHS, it's removed/combined so that I cannot match vector_shuffle in the instruction selector. If the vector_shuffle is combined, I have to write the instruction selector like these: def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1), [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0), (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)] def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1), [sub REG:$src0, (vector_shuffle REG:$src1, REG:$s...

Printing without this could lead to the following output, while the values are not exactly zero: IMM[5] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} IMM[6] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} IMM[7] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} when printing the values as hex, we can now see the differences: IMM[5] FLT32 {0x00000019, 0x0000000f, 0x00000005, 0...

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return isInt<3...

...output from the debug command: fixmele:CoRegisterMessageFilter stub fixme:win:EnumDisplayDevicesW ((null),0,0x7fb0f7e8,0x00000000), stub! fixmele:ITypeInfo_fnRelease destroy child objects fixmeowermgnt:SetThreadExecutionState (0x80000000): stub, harmless. fixmele:CoRegisterMessageFilter stub fixme:imm:ImmGetOpenStatus (0x79578600): semi-stub fixme:imm:ImmReleaseContext (0x20026, 0x79578600): stub fixme:imm:ImmGetOpenStatus (0x79578600): semi-stub fixme:imm:ImmReleaseContext (0x20026, 0x79578600): stub fixme:imm:ImmGetOpenStatus (0x79578600): semi-stub fixme:imm:ImmReleaseContext (0x30076, 0x7957...

...h the iterator invalidation. However, looking at other peephole optimizers passes, I couldn't see how to do this: #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; ++MFI) { MachineBasicBlock* MBB = MFI; for (MachineBasicBlock::iterator MBBI = MBB->begin(); MBBI != MBB->end(); ++MBBI) { MachineInstr *NewMI = NULL; OldMI = MBBI; //...