search for: iseldagtodag

...// Reshuffle LDW's results so that the first two match LOAD's > result > // type > SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2), > SDValue(LDW, 1) }; > SDNode* NN = CurDAG->getMergeValues(Unpack, SDLoc(N)).getNode(); Calling getMergeValues in ISelDAGToDAG is a bad idea; there aren't supposed to be any MERGE_VALUES nodes at that point in the pipeline. You can call ReplaceUses with SDValues rather than SDNodes. -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Found...

...ay LLVM-Dev, I hope all are in good health. We are currently implementing the compare operation for i64 type in our target. The main difference of the i64 type compare to lower integer types is that it performs a library call instead of generating a compare instruction. All is good until before ISelDAGToDAG class. We have observed that the difference in a compare operation for i32 and i64 types is that, the 4th DAG node of the BRCOND node is glued for the i32 type and not glued in the i64 type. Please refer to the boxed nodes in the attached DAGs for a better visualization. Also, upon entering the IS...

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions

...y, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions. The issue appears when trying to use the SP in iSelLowering, in particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only ha...

...mbly instructions: MOV R0, #A // R0 pointing to address of A MOV R1, #B // R1 pointing to address of B ADD *R0, *R1 // Adding both memory operands MOV #C, *R0 // Moving result to address of C How should i define such mov and add instruction in my .td files? How will ISD::LOAD be seleted in ISelDAGtoDAG in select() function? I want to start with simple .td definitions and would later like to encapsulate them in multiclass once basic example works. Can someone please help how to achieve this? Regards, Alex -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://...

...hat's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the register class to identify the type, potentially in ISelDAGToDag.cpp or is there a better place for this to be done? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150127/4f69073d/attachment.html>

...was renamed at some time (which makes sense, since I don't think that the TargetLowering classes have anything to do with instruction selection [any more?]). However, the inconsistent filenames are a bit confusing. Perhaps somebody should rename the lot of them? The same goes for <Target>ISelDAGToDAG.cpp, which defines a class called <Target>DAGToDAGISel. Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 189 bytes Desc: Digital signature URL: <http://lists.llvm.org/pipermail/llvm-dev/at...

I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG' implementation. But it seems to me that I ought to be able to achieve this exclusively using TableGen with minimal custom C++ code, but I can't quite get the patterns to work to achieve this. I have two types of post-increment: 1. increment by an implied constant which is the...

...ge that to a zext or sext node based on signed or unsigned? > > I'm fairly unfamiliar with SelectionDAG process (outside of the docs on > llvm website). > > It seems like I should be able to insert a custom hook using the > register class to identify the type, potentially in ISelDAGToDag.cpp or is > there a better place for this to be done? > > Thanks. > > > It sounds to me like you are looking for the AssertSext / AssertZext nodes > > -Matt > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperm...

Hello. I am using the post-RA (Register Allocation) scheduler to avoid data hazards by inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart some sequences of instructions which should remain "glued" together. More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for example a BUILD_VECTOR with a machine SDNode called VLOAD_D_WO_IMM and an INLINEASM, the latter having a simple dataflow dependence (black solid edge when outputting the DAG as a .DOT after instruction selection) on the result of the former instruction. (I c...

...have anything to do with > instruction selection [any more?]). However, the inconsistent > filenames are a > bit confusing. Perhaps somebody should rename the lot of them? Sure, I'd support renaming them to <target>TargetLowering.cpp etc. > The same goes for <Target>ISelDAGToDAG.cpp, which defines a class > called > <Target>DAGToDAGISel. The DAGToDAG suffix is actually a pretty old historical artifact at this point. It would be better to rename the classes and files to <target>DAGISel. -Chris

Are there any known examples of a backend using a function pass, not a machine function pass, to do LLVM-LLVM transformations right before ISelDagToDag? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091005/81ec49f9/attachment.html>

Current ISelDagToDag is created once per module. The TargetLowering class is allocated there and register classes are added and the computeRegisterProperties is called. In order to switch back and forth between mips16 and mips32, I need to be able to reset what is done during computerRegisterProperties. Has anyone...

...sed on signed or >> unsigned? >> >> I'm fairly unfamiliar with SelectionDAG process (outside of the docs on >> llvm website). >> >> It seems like I should be able to insert a custom hook using the >> register class to identify the type, potentially in ISelDAGToDag.cpp or is >> there a better place for this to be done? >> >> Thanks. >> >> >> It sounds to me like you are looking for the AssertSext / AssertZext >> nodes >> >> -Matt >> > > > -------------- next part -------------- An HTML att...

Hi I am looking at some of the existing targets to try to understand more about writing a backend. I was a little puzzled by the use of a method ReplaceUses in *ISelDAGToDAG.cpp (*= most targets, e.g. ARM, X86..). I found its definition in the *GenDAGISel.inc file that is autogenerated from the target description. I can only assume TableGen emits this method definition for every traget. Is this method implementation, in some way that I cannot see, specific to...

I am trying to removing a load to a TargetGlobalAddress in ISelDagToDag that my backend does not support. The TargetGlobalAddress is assumed to always be of ConstantInt or ConstantFP type, so this transformation is valid. I am correctly able to modify the dag and remove all of the uses of the node as specified in the attached before and after dot images. The nodes in q...

To generate code for a target which doesn't have immediate constant as instruction operand, do I (the target specific back-end, XXXTarget) need to provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1) to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my XXXTargetLowering::LowerOperation, or LLVM target-independent framework can do such transformation

I'm trying to replace SDIvRem (whch returns two i16 types) with a custom that returns i32 or i16. I am getting the Assertion (!Node || ResNo < Node->getNumValues() && "Invalid result number for the given node!") Seems that it doesn't like returning one value but how do you return more than one value? I am doing this in the LowerOperation for the case SDIVREM and a

...and adds > that register with another memory location. > > My target loads the address of the memory locations in the registers > for both the operands and then uses add operation on the registers in > an indirect way. How do I specify that in .td files so that it matches > in ISelDAGToDAG select() function? Any small example? > Oh, you mean the result goes into memory, not a register? So, something like the following: define void @foo(i32 *%a) { entry: %0 = load i32, i32* %a, align 4 %add = add i32 %0, 3 store i32 %add, i32* %a, align 4 ret void } On x86, this ge...

...] Just setting the Action to Expand here via setOperationAction(ISD::Constant,MVT::i64,Expand); does not solve the problem. I took a look into your AMDIL-patch and found out that your target supports this operation. I have the feeling that this has to be lowered manually or has to be handled by ISelDAGtoDAG or similar. Well, I guess I have to dig a little bit deeper. If you have any other suggestion - I definitely am interested ;-) Ciao, Fabian