Displaying 20 results from an estimated 66 matches for "insert_subreg".
2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as an operand somewh...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
> sub-register type, e.g. i8.
>
> >
> > Can I use to set a superreg of i16 ty...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
return *I;
assert(false && "Couldn't find the register class");
return 0;
}
-----------------------------------------------------------------
The getSubRegisterRegClass uses SubIdx - 1;
so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because getSubRegisterRegClass will fail.(GR16_ does not have a SubRegClass at index -1.)
OTOH, if you use SubIdx as 1, both in SubRegSet and x86_subreg_8bit, the INSERT_SUBREG (IMPLICIT_DEF, AL, 1) will work.
But then INSERT_SUBREG (AX, AH, 2) will not work...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>
>
> class GR16_ ..... {
> let SubRegClassList = [GR8];
> }
Right. Subreg index starts from 1. This ought to be fixed but it's not
(yet).
>
>
> The getSubRegisterRegClass uses SubIdx - 1;
>
> so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> getSubRegisterRegClass will fail.(GR16_ does not have a SubRegClass
> at index -1.)
>
> OTOH, if you use SubIdx as 1, both in SubRegSet and x86_subreg_8bit,
> the INSERT_SUBREG (IMPLICIT_DEF, AL, 1) will work.
Ok.
>
>
>...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...ry elegant. We'll clean it up
some day.
Evan
On Oct 13, 2008, at 11:24 AM, sanjiv gupta wrote:
> On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>>
>> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>>
>>> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>>
>>
>> No, insert_subreg returns a value:
>>
>>
>> v1 = insert_subreg v2, v3, idx
>>
>>
>> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>> sub-register type, e.g. i8.
>>
>>>
>>...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...> >
> > class GR16_ ..... {
> > let SubRegClassList = [GR8];
> > }
>
> Right. Subreg index starts from 1. This ought to be fixed but it's not
> (yet).
>
> >
> >
> > The getSubRegisterRegClass uses SubIdx - 1;
> >
> > so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because
> > getSubRegisterRegClass will fail.(GR16_ does not have a SubRegClass
> > at index -1.)
> >
> > OTOH, if you use SubIdx as 1, both in SubRegSet and x86_subreg_8bit,
> > the INSERT_SUBREG (IMPLICIT_DEF, AL, 1) will wo...
2012 Jul 18
1
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
...er pair forming the 64bit register. For the PPC-backend this
is no problem as it has true 64bit register, this however is not the
case for the TriCore. So I need to get the vritual register (pair)
that will be used to store the 64bit value to access its subregisters.
2. Use a pattern consisting of INSERT_SUBREG-nodes
A colleague of mine (who originally implemented the TriCore-backend)
suggested to use a pattern that replaces 64bit-constants by tow
INSERT_SUBREG-nodes. I ended up having the following pattern:
def : Pat<(i64 imm:$imm),
(INSERT_SUBREG
(INSERT_SUBREG
(i64 (IMPLICIT_...
2008 Mar 19
2
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
The new SUBREG target-independent instructions aren't getting
mayLoad/mayStore flags set correctly.
For example, in the generated X86GenInstrInfo.inc file,
there is only one entry for INSERT_SUBREG:
{ 5, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL,
OperandInfo107 }, // Inst #5 = INSERT_SUBREG
THe sixth field is zero, which means it doesn't have the the
MayLoad flag set.
x86-64 does have a few variants of INSERT_SUBREG, and one of
them does have a load:
d...
2010 Jul 28
3
[LLVMdev] Subregister coalescing
...l the vector register elements
are directly accesible, so VI1 reg (Vector Integer 1) has I4, I5, I6 and
I7 as its (integer) subregisters. Subregisters of same reg *never*
overlap.
Therefore, vector loads are lowered to scalar loads followed by a chain
of INSERT_VECTOR_ELTs. Then we select those to INSERT_SUBREG, everything
fine to that point.
Status before live analisys is (non-related instrs removed):
36 %reg16388<def> = LDWr %reg16384, 0; mem:LD4[<unknown>]
68 %reg16392<def> = INSERT_SUBREG %reg16392<undef>, %reg16388<kill>, 1
76 %reg16394<def> = LDWr %reg16386<k...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...f the high 8-bit sub-registers.
>> We
>> are leaving some performance on the table. We'll probably fix it one
>> day. However, this doesn't apply to your target, right? There is
>> nothing preventing you from specifying the sub-registers and making
>> use of insert_subreg, no?
>>
>> Evan
>>
> it is, though we have a workaround.
>
> We have 16-bit registers class and want to set both the lo and high
> parts using INSERT_SUBREG.
>
> The workaround is to declare the same SubRegClass twice while
> declaring
> the SuperRegister...
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...sters.
> >> We
> >> are leaving some performance on the table. We'll probably fix it one
> >> day. However, this doesn't apply to your target, right? There is
> >> nothing preventing you from specifying the sub-registers and making
> >> use of insert_subreg, no?
> >>
> >> Evan
> >>
> > it is, though we have a workaround.
> >
> > We have 16-bit registers class and want to set both the lo and high
> > parts using INSERT_SUBREG.
> >
> > The workaround is to declare the same SubRegClass twice...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...gt;>> are leaving some performance on the table. We'll probably fix it
>>>> one
>>>> day. However, this doesn't apply to your target, right? There is
>>>> nothing preventing you from specifying the sub-registers and making
>>>> use of insert_subreg, no?
>>>>
>>>> Evan
>>>>
>>> it is, though we have a workaround.
>>>
>>> We have 16-bit registers class and want to set both the lo and high
>>> parts using INSERT_SUBREG.
>>>
>>> The workaround is to declare...
2008 Mar 19
0
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
On Mar 18, 2008, at 6:12 PM, Dan Gohman wrote:
> The new SUBREG target-independent instructions aren't getting
> mayLoad/mayStore flags set correctly.
>
> For example, in the generated X86GenInstrInfo.inc file,
> there is only one entry for INSERT_SUBREG:
>
> { 5, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL,
> OperandInfo107 }, // Inst #5 = INSERT_SUBREG
>
> THe sixth field is zero, which means it doesn't have the the
> MayLoad flag set.
I am not sure I understand. INSERT_SUBREG shouldn't have...
2012 Jul 12
0
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
On Thu, Jul 12, 2012 at 01:22:39PM +0200, Fabian Scheler wrote:
> Hi Micah,
>
> > We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
> >
> > What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
>
> thanks for your hint. Unfortunately, I didn't find any
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
%vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
%vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
%vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2
%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg12...
2012 Jul 12
2
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
Hi Micah,
> We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer
2011 May 20
1
[LLVMdev] subregisters, def-kill
If I write
%reg16506<def> = INSERT_SUBREG %reg16506, %reg16445, hi16; #1
%reg16506<def> = INSERT_SUBREG %reg16506, %reg16468, lo16; #2
store %reg16506 #3
it will not coalesce, as
LiveVariables:
on
#2: %16506 gets #2 as a kill
#3: %16506 gets...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%T1_Z; R600_TReg32:%vreg16
> %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
> %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
> %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
> %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2
> %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
> %vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, se...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...reg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2
%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10
%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6
RESERVE_REG 1
RESERVE_REG 2
%vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8
%vreg13<def> = IMPLICIT_DEF; R600_Reg...