search for: tricor

...as "legalization" that will >>> transform this into something sane for your target automatically. I >>> would suggest not ignoring this because the optimizers will >>> occasionally generate unusual loads and stores. >> >> Hm, my problem is that the TriCore does not really support i64 only >> paired 32.bit registers, but I need such a register class as some >> instructions require them. So, the Legalizer thinks i64-instructions >> are legal and integer types above i32 are not legalized automatically. >> For the most operations...

Hi Fabian, Anton, On 22/08/2012 08:25, Fabian Scheler wrote: >>> here are the definitions of these register classes: >>> >>> // Data register class >>> def DR : RegisterClass<"TriCore", [i32], 32, >>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>> D8, D9, D10, D11, D12, D13, D14, D15)>; >>> >>> // Extended-size data register class >>> def ER : RegisterClass<"TriCore&...

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER : RegisterClass<"TriCore", [i64], 32, >...

Hi LLVM-Folks, at our department we have an in-house developed back-end for the TriCore processor and we want to upgrade it to LLVM 3.1. However, we have some troubles regarding some instructions that work on 64bit registers: The TriCore processor has 16 32bit registers that can be paired to form 64bit registers. Except a few instructions all work on 32bit registers, thus the TriCor...

...gt;>>>> transform this into something sane for your target automatically. I >>>>> would suggest not ignoring this because the optimizers will >>>>> occasionally generate unusual loads and stores. >>>> >>>> Hm, my problem is that the TriCore does not really support i64 only >>>> paired 32.bit registers, but I need such a register class as some >>>> instructions require them. So, the Legalizer thinks i64-instructions >>>> are legal and integer types above i32 are not legalized automatically. >>...

...on" that will >>>> transform this into something sane for your target automatically. I >>>> would suggest not ignoring this because the optimizers will >>>> occasionally generate unusual loads and stores. >>> >>> Hm, my problem is that the TriCore does not really support i64 only >>> paired 32.bit registers, but I need such a register class as some >>> instructions require them. So, the Legalizer thinks i64-instructions >>> are legal and integer types above i32 are not legalized automatically. >>> For the...

Hi Eli, thank you for the information. >> thanks to kind help of the LLVM-community I was able to bring my >> TriCore back-end a huge step forward, however I am not done, so far. I >> still miss the following features and maybe you could again provide me >> some help: >> >> 1. Passing return values on the stack >> >> Describing the calling conventions in tablegen so that first...

>> here are the definitions of these register classes: >> >> // Data register class >> def DR : RegisterClass<"TriCore", [i32], 32, >> (add D0, D1, D2, D3, D4, D5, D6, D7, >> D8, D9, D10, D11, D12, D13, D14, D15)>; >> >> // Extended-size data register class >> def ER : RegisterClass<"TriCore", [i64], 32, >...

Hi Devs, I am planning to start working on Tricore backend in LLVM Toolchain with the hope of upstreaming it. This particular mail is about enquiring whether someone is already doing this job or not. If someone already started work, I would also like to contribute/help to complete it soon. thank you ./kamlesh

It appears that someone is working on it. https://github.com/TriDis/llvm-tricore

Hello Dear Team, I wanted to know in which version of LLVM Tricore architecture is supported. I have LLVM 2.8 with me which has no support for Tricore. Basically I wanted to add Aurix target support. Could you please help me. Best Regards / Mit freundlichen Grüßen Minal Kulkarni Knorr Bremse Technology Center India Survey No.276, Village Mann, Hinjewadi, Ph...

On Thu, Aug 16, 2012 at 11:48 PM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi Eli, > > thank you for the information. > >>> thanks to kind help of the LLVM-community I was able to bring my >>> TriCore back-end a huge step forward, however I am not done, so far. I >>> still miss the following features and maybe you could again provide me >>> some help: >>> >>> 1. Passing return values on the stack >>> >>> Describing the calling conventions in...

...gt; transform this into something sane for your target automatically. I >>>>>> would suggest not ignoring this because the optimizers will >>>>>> occasionally generate unusual loads and stores. >>>>> >>>>> Hm, my problem is that the TriCore does not really support i64 only >>>>> paired 32.bit registers, but I need such a register class as some >>>>> instructions require them. So, the Legalizer thinks i64-instructions >>>>> are legal and integer types above i32 are not legalized automatical...

Hi everybody, thanks to kind help of the LLVM-community I was able to bring my TriCore back-end a huge step forward, however I am not done, so far. I still miss the following features and maybe you could again provide me some help: 1. Passing return values on the stack Describing the calling conventions in tablegen so that first registers are used and to fall back to the stack if...

...http://www.knorr-bremse.com/> From: Johannes Doerfert <johannesdoerfert at gmail.com> Sent: Thursday, May 28, 2020 10:20 PM To: Kulkarni, Minal <Minal.Kulkarni at knorr-bremse.com>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] LLVM Support needed I don't think we have a Tricore backend, at least not public in mainline LLVM. I might be wrong though. FWIW, LLVM 2.8 is *really* old. Cheers, Johannes On 5/27/20 11:56 PM, Kulkarni, Minal via llvm-dev wrote: Hello Dear Team, I wanted to know in which version of LLVM Tricore architecture is supported. I have...

...> Sent: Wednesday, June 13, 2012 4:05 AM > To: LLVM Developers Mailing List > Subject: [LLVMdev] Instructions working on 64bit registers without true > support for 64bit operations > > Hi LLVM-Folks, > > at our department we have an in-house developed back-end for the > TriCore processor and we want to upgrade it to LLVM 3.1. However, we > have some troubles regarding some instructions that work on 64bit > registers: > > The TriCore processor has 16 32bit registers that can be paired to > form 64bit registers. Except a few instructions all work on 32bit &...

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty

...o not have any valut type which > defines 3xi64. > However, the paired register needs to have type. > > Fabian, what are the definitions of ER and DR register classes? Hi Anton, here are the definitions of these register classes: // Data register class def DR : RegisterClass<"TriCore", [i32], 32, (add D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15)>; // Extended-size data register class def ER : RegisterClass<"TriCore", [i64], 32, (add E0, E2, E4, E6, E8,...

...nllopard at gmail.com>: > Hi Fabian, Anton, > > > On 22/08/2012 08:25, Fabian Scheler wrote: >>>> >>>> here are the definitions of these register classes: >>>> >>>> // Data register class >>>> def DR : RegisterClass<"TriCore", [i32], 32, >>>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>>> D8, D9, D10, D11, D12, D13, D14, D15)>; >>>> >>>> // Extended-size data register class >>>> def ER : RegisterCla...

On Thu, Aug 16, 2012 at 5:18 AM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi everybody, > > thanks to kind help of the LLVM-community I was able to bring my > TriCore back-end a huge step forward, however I am not done, so far. I > still miss the following features and maybe you could again provide me > some help: > > 1. Passing return values on the stack > > Describing the calling conventions in tablegen so that first registers > are used...