Hi,
I have a problem with creating a MFENCE on X86 with SSE
In X86InstrSSE.td, a MFENCE is
def MFENCE : I<0xAE, MRM6m, (outs), (ins),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<
[HasSSE2]>;
In X86CodeEmitter.cpp in emitInstruction
case X86II::MRM6m: case X86II::MRM7m: {
intptr_t PCAdj = (CurOp+4 != NumOps) ?
(MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm
(Desc) : 4) : 0;
...
If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so
we to get the 4th operand from the MFENCE operation which has no
operands so we get an error. I'm not sure what this code is trying to
do. Should the condition be < NumOps?
Thanks,
-- Mon Ping
Hmm. mfence and lfence needs special handling. I'll take a look. Evan On Oct 16, 2008, at 10:46 PM, Mon Ping Wang wrote:> Hi, > > I have a problem with creating a MFENCE on X86 with SSE > > In X86InstrSSE.td, a MFENCE is > def MFENCE : I<0xAE, MRM6m, (outs), (ins), > "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< > [HasSSE2]>; > > In X86CodeEmitter.cpp in emitInstruction > > case X86II::MRM6m: case X86II::MRM7m: { > intptr_t PCAdj = (CurOp+4 != NumOps) ? > (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm > (Desc) : 4) : 0; > ... > > If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so > we to get the 4th operand from the MFENCE operation which has no > operands so we get an error. I'm not sure what this code is trying to > do. Should the condition be < NumOps? > > Thanks, > -- Mon Ping > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
I've fixed this (untested though). http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20081013/068611.html Evan On Oct 17, 2008, at 9:51 AM, Evan Cheng wrote:> Hmm. mfence and lfence needs special handling. I'll take a look. > > Evan > > On Oct 16, 2008, at 10:46 PM, Mon Ping Wang wrote: > >> Hi, >> >> I have a problem with creating a MFENCE on X86 with SSE >> >> In X86InstrSSE.td, a MFENCE is >> def MFENCE : I<0xAE, MRM6m, (outs), (ins), >> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< >> [HasSSE2]>; >> >> In X86CodeEmitter.cpp in emitInstruction >> >> case X86II::MRM6m: case X86II::MRM7m: { >> intptr_t PCAdj = (CurOp+4 != NumOps) ? >> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm >> (Desc) : 4) : 0; >> ... >> >> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so >> we to get the 4th operand from the MFENCE operation which has no >> operands so we get an error. I'm not sure what this code is trying >> to >> do. Should the condition be < NumOps? >> >> Thanks, >> -- Mon Ping >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev