search for: mrm7m

...a problem with creating a MFENCE on X86 with SSE In X86InstrSSE.td, a MFENCE is def MFENCE : I<0xAE, MRM6m, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< [HasSSE2]>; In X86CodeEmitter.cpp in emitInstruction case X86II::MRM6m: case X86II::MRM7m: { intptr_t PCAdj = (CurOp+4 != NumOps) ? (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm (Desc) : 4) : 0; ... If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so we to get the 4th operand from the MFENCE operation which has no operands so we get a...

...with SSE > > In X86InstrSSE.td, a MFENCE is > def MFENCE : I<0xAE, MRM6m, (outs), (ins), > "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< > [HasSSE2]>; > > In X86CodeEmitter.cpp in emitInstruction > > case X86II::MRM6m: case X86II::MRM7m: { > intptr_t PCAdj = (CurOp+4 != NumOps) ? > (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm > (Desc) : 4) : 0; > ... > > If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so > we to get the 4th operand from the MFENCE operation which h...

...InstrSSE.td, a MFENCE is >> def MFENCE : I<0xAE, MRM6m, (outs), (ins), >> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< >> [HasSSE2]>; >> >> In X86CodeEmitter.cpp in emitInstruction >> >> case X86II::MRM6m: case X86II::MRM7m: { >> intptr_t PCAdj = (CurOp+4 != NumOps) ? >> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm >> (Desc) : 4) : 0; >> ... >> >> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so >> we to get the 4th operand from the...

Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], IIC_SSE_PREFETCH>, PD; let Predicates = [HasCLWB], SchedRW = [WriteLoad] in def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",...

...l.com> wrote: > Here's a couple examples for mapping an intrinsic to an X86 instruction > from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can > find others. > > let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in > def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), > "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], > IIC_SSE_PREFETCH>, PD; > > let Predicates = [HasCLWB], SchedRW = [WriteLoad] in > def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), &quot...

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to

...t; Here's a couple examples for mapping an intrinsic to an X86 instruction >> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can >> find others. >> >> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in >> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), >> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], >> IIC_SSE_PREFETCH>, PD; >> >> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in >> def CLWB : I<0xAE, MRM6m, (outs), (in...

...REX |= 1 << Bit; > - Bit++; > - } > - } > - break; > - } > - case X86II::MRM0m: case X86II::MRM1m: > - case X86II::MRM2m: case X86II::MRM3m: > - case X86II::MRM4m: case X86II::MRM5m: > - case X86II::MRM6m: case X86II::MRM7m: > - case X86II::MRMDestMem: { > - unsigned e = isTwoAddr ? 5 : 4; > - i = isTwoAddr ? 1 : 0; > - if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) > - REX |= 1 << 2; > - unsigned Bit = 0; > - for (; i != e; ++i) { >...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...le examples for mapping an intrinsic to an X86 instruction >>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can >>> find others. >>> >>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in >>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), >>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], >>> IIC_SSE_PREFETCH>, PD; >>> >>> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in >>> def CLWB : I<0xAE...

...encoded in bits [7:4] of an immediate. Memory is the 4th operand. Rarely used. MRMXm - modrm.mod==0x3, with a value of 0 in modrm[5:3]. modrm[2:0] and optional sib byte and displacement encode memory address. This is almost the same as MRM0m, but the disassembler ignores modrm[5:3] MRM0m-MRM7m - modrm.mod!=0x3, with a fixed value(0-7) in modrm[5:3]. modrm[2:0] and optional sib byte and displacement encode memory address. MRMDestReg - modrm.mod==0x3, modrm[2:0] encodes destination register. if vex.vvvv is used encodes the next register, mrm[5:3] encodes the second or third registe...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML