Displaying 5 results from an estimated 5 matches for "pcadj".
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padj
2008 Oct 17
2
[LLVMdev] MFENCE encoding
...g a MFENCE on X86 with SSE
In X86InstrSSE.td, a MFENCE is
def MFENCE : I<0xAE, MRM6m, (outs), (ins),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<
[HasSSE2]>;
In X86CodeEmitter.cpp in emitInstruction
case X86II::MRM6m: case X86II::MRM7m: {
intptr_t PCAdj = (CurOp+4 != NumOps) ?
(MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm
(Desc) : 4) : 0;
...
If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so
we to get the 4th operand from the MFENCE operation which has no
operands so we get an error. I'm not...
2008 Oct 17
0
[LLVMdev] MFENCE encoding
...InstrSSE.td, a MFENCE is
> def MFENCE : I<0xAE, MRM6m, (outs), (ins),
> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<
> [HasSSE2]>;
>
> In X86CodeEmitter.cpp in emitInstruction
>
> case X86II::MRM6m: case X86II::MRM7m: {
> intptr_t PCAdj = (CurOp+4 != NumOps) ?
> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm
> (Desc) : 4) : 0;
> ...
>
> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so
> we to get the 4th operand from the MFENCE operation which has no
> operands so we...
2008 Oct 17
1
[LLVMdev] MFENCE encoding
...> def MFENCE : I<0xAE, MRM6m, (outs), (ins),
>> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<
>> [HasSSE2]>;
>>
>> In X86CodeEmitter.cpp in emitInstruction
>>
>> case X86II::MRM6m: case X86II::MRM7m: {
>> intptr_t PCAdj = (CurOp+4 != NumOps) ?
>> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm
>> (Desc) : 4) : 0;
>> ...
>>
>> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so
>> we to get the 4th operand from the MFENCE operation which has n...
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
...> Index: lib/Target/X86/X86CodeEmitter.cpp
> ===================================================================
> --- lib/Target/X86/X86CodeEmitter.cpp (revision 49716)
> +++ lib/Target/X86/X86CodeEmitter.cpp (working copy)
> @@ -92,8 +92,6 @@
> intptr_t PCAdj = 0);
>
> unsigned getX86RegNum(unsigned RegNo) const;
> - bool isX86_64ExtendedReg(const MachineOperand &MO);
> - unsigned determineREX(const MachineInstr &MI);
>
> bool gvNeedsLazyPtr(const GlobalValue *GV);
> };
> @@ -405,139 +403,6 @@
> }
>...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And