search for: x86ii

...ineOperand &MO); > - unsigned determineREX(const MachineInstr &MI); > > bool gvNeedsLazyPtr(const GlobalValue *GV); > }; > @@ -405,139 +403,6 @@ > } > } > > -static unsigned sizeOfImm(const TargetInstrDesc *Desc) { > - switch (Desc->TSFlags & X86II::ImmMask) { > - case X86II::Imm8: return 1; > - case X86II::Imm16: return 2; > - case X86II::Imm32: return 4; > - case X86II::Imm64: return 8; > - default: assert(0 && "Immediate size not set!"); > - return 0; > - } > -} > - > -/// isX86...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...m to be operands held in order by the MachineInstr, from an offset onwards - Base, Scale, Index, Displacement, Segment. The former, if I understand it correctly, is used to hold a relationship back to IR load/store instructions. Is it possible to have a X86 MachineInstr with a memory operand (i.e. X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? What about the reverse? Thanks, Mircea. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180308/e27ca0e4/attachment.html>

...ey can write code like: > const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); > const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); for both MachineInstrs and MCInsts. > > Is it possible to have a X86 MachineInstr with a memory operand (i.e. X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? What about the reverse? > * Attaching a MachineMemOperand to an instruction that doesn’t reference any memory: From what I tried, the instruction has to be marked as “mayLoad / mayStore” (you can see them in X86InstrInfo.td) in order...

Hi, I have a problem with creating a MFENCE on X86 with SSE In X86InstrSSE.td, a MFENCE is def MFENCE : I<0xAE, MRM6m, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< [HasSSE2]>; In X86CodeEmitter.cpp in emitInstruction case X86II::MRM6m: case X86II::MRM7m: { intptr_t PCAdj = (CurOp+4 != NumOps) ? (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm (Desc) : 4) : 0; ... If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so we to get the 4th operand from the MFENCE operation which has...

Thanks for the details! How should we think of the case where an instruction has memory operands (in the sense that X86II::getMemoryOperandNo >=0), but doesn't have MachineMemOperands? I'm seeing an example in the case of __builtin_prefetch (lowered via SelectionDAG::getMemIntrinsicNode, which produces a MachineMemOperand) vs __builtin_ia32_gatherpfdpd, lowered through getPrefetchNode in X86ISelLowering.cp...

...ef P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; now getting no error. please tell me whether my method is correct? Also please confirm this whether i need to make changes in MC framework to emit binary code of my vector instructions. So far i made no changes...

...ate size UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86BaseInfo.h:574! i made extensive use of gdb and after debugging i found the line with issue in X86MCCodeEmitter.cpp. Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. then, the following code gets executed; case X86II::MRMDestReg: { EmitByte(BaseOpcode, CurByte, OS); unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 EmitRegModRMByte(MI.getOperand(CurOp), GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); CurOp = SrcRegNum + 1; break; } so here CurOp becomes 2. After this;...

..., (ins >> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >> >> so i defined; >> >> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >> >> then used this condition; >> >> if(HasTA) >> ++SrcRegNum; >> >> now getting no error. >> >> please tell me whether my method is correct? Also please confirm this >> whether i need to make changes in...

...),"P_256B_VADD\t{$src1, $src2, >>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >>>> >>>> so i defined; >>>> >>>> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >>>> >>>> then used this condition; >>>> >>>> if(HasTA) >>>> ++SrcRegNum; >>>> >>>> now getting no error. >>>> >>>> please tell me whether my method is corr...

...h creating a MFENCE on X86 with SSE > > In X86InstrSSE.td, a MFENCE is > def MFENCE : I<0xAE, MRM6m, (outs), (ins), > "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< > [HasSSE2]>; > > In X86CodeEmitter.cpp in emitInstruction > > case X86II::MRM6m: case X86II::MRM7m: { > intptr_t PCAdj = (CurOp+4 != NumOps) ? > (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm > (Desc) : 4) : 0; > ... > > If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so > we to get the 4th operand from th...

...E >> >> In X86InstrSSE.td, a MFENCE is >> def MFENCE : I<0xAE, MRM6m, (outs), (ins), >> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< >> [HasSSE2]>; >> >> In X86CodeEmitter.cpp in emitInstruction >> >> case X86II::MRM6m: case X86II::MRM7m: { >> intptr_t PCAdj = (CurOp+4 != NumOps) ? >> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm >> (Desc) : 4) : 0; >> ... >> >> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so >> we to ge...

I was getting same error when i keep both EVEX/EVEX_4V and TA. So, i restored my original instructions and for that i have to include bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; in order to emit binary correctly. Is it right? On Tue, Sep 5, 2017 at 5:45 AM, Craig Topper <craig.topper at gmail.com> wrote: > Put the TA's back. EVEX/EVEX_4V does not replace TA. They are for...

...ot;, [(set VRP_2048:$dst, (add (v64i32 >>>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >>>>>>>> >>>>>>>> so i defined; >>>>>>>> >>>>>>>> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >>>>>>>> >>>>>>>> then used this condition; >>>>>>>> >>>>>>>> if(HasTA) >>>>>>>> ++SrcRegNum; >>>>>>>> >>>>&...

...>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >>>>>> >>>>>> so i defined; >>>>>> >>>>>> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >>>>>> >>>>>> then used this condition; >>>>>> >>>>>> if(HasTA) >>>>>> ++SrcRegNum; >>>>>> >>>>>> now getting no error. >>>>&g...

On Mar 23, 2009, at 12:57 PM, David A. Greene wrote: > I'm looking at the instruction formats and I can't grok the > comments. For > example: > > // SSSE3 Instruction Templates: > // > // SS38I - SSSE3 instructions with T8 prefix. > // SS3AI - SSSE3 instructions with TA prefix. > // > > Where are these prefix names coming from? I can't find any

I'm looking at the instruction formats and I can't grok the comments. For example: // SSSE3 Instruction Templates: // // SS38I - SSSE3 instructions with T8 prefix. // SS3AI - SSSE3 instructions with TA prefix. // Where are these prefix names coming from? I can't find any mention of them in the Intel literature. Also, there's this curious table: // Prefix byte classes

.../x86_64-linux-gnu/libpthread.so.0+0x10d10) #5 0x00007f2f2adc2267 gsignal (/lib/x86_64-linux-gnu/libc.so.6+0x35267) #6 0x00007f2f2adc3eca abort (/lib/x86_64-linux-gnu/libc.so.6+0x36eca) #7 0x000000000195f6c0 LLVMInstallFatalErrorHandler lib/Support/ErrorHandling.cpp:133:0 #8 0x0000000000c08966 llvm::X86II::getSizeOfImm(unsigned long) lib/Target/X86/MCTargetDesc/X86BaseInfo.h:577:29 #9 0x0000000000c04c2a (anonymous namespace)::X86MCCodeEmitter::encodeInstruction(llvm::MCInst const&, llvm::raw_ostream&, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const li...

...o indicate instructions that can be folded with the user of the register by changing the user to an immediate instruction. And it wouldn't be set on an instruction like "addl $0, %eax" or "addl $0, (%ecx)" either since those aren't moves. For X86 you can try using "X86II::hasImm(MI.getDesc().TSFlags)" that's what the encoder uses to determine if there's an immediate to encode at the end of the instruction encoding. ~Craig On Fri, Feb 9, 2018 at 1:13 PM, S. Bharadwaj Yadavalli <bharadwajy at gmail.com > wrote: > I am trying to categorize...

I am trying to categorize the machine instructions based on associated static (i.e., as encoded in .td file) machine description and the corresponding APIs. I would like to perform appropriate actions based on the kind of instruction in a tool that I am working on. For example, I'd like to distinguish between memop instructions involving immediate vs register. While it appears that I would be