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...%R_0_REG2048b_0<kill> I am getting the following error: Unknown immediate size UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86BaseInfo.h:574! i made extensive use of gdb and after debugging i found the line with issue in X86MCCodeEmitter.cpp. Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. then, the following code gets executed; case X86II::MRMDestReg: { EmitByte(BaseOpcode, CurByte, OS); unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 EmitRegModRMByte(MI.getOperand(CurOp), GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);...

...gt; Unknown immediate size >> UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86BaseInfo.h:574! >> >> >> i made extensive use of gdb and after debugging i found the line with >> issue in X86MCCodeEmitter.cpp. >> >> Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. >> >> then, the following code gets executed; >> >> case X86II::MRMDestReg: { >> EmitByte(BaseOpcode, CurByte, OS); >> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >> EmitRegModRMByte(MI.getOperand(CurOp), >>...

...executed at /lib/Target/X86/MCTargetDesc/X86BaseInfo.h:574! >>>> >>>> >>>> i made extensive use of gdb and after debugging i found the line with >>>> issue in X86MCCodeEmitter.cpp. >>>> >>>> Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. >>>> >>>> then, the following code gets executed; >>>> >>>> case X86II::MRMDestReg: { >>>> EmitByte(BaseOpcode, CurByte, OS); >>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>>...

...Info.h:574! >>>>>> >>>>>> >>>>>> i made extensive use of gdb and after debugging i found the line >>>>>> with issue in X86MCCodeEmitter.cpp. >>>>>> >>>>>> Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. >>>>>> >>>>>> then, the following code gets executed; >>>>>> >>>>>> case X86II::MRMDestReg: { >>>>>> EmitByte(BaseOpcode, CurByte, OS); >>>>>> unsigned SrcReg...

...;>>>>>>> >>>>>>>> i made extensive use of gdb and after debugging i found the line >>>>>>>> with issue in X86MCCodeEmitter.cpp. >>>>>>>> >>>>>>>> Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. >>>>>>>> >>>>>>>> then, the following code gets executed; >>>>>>>> >>>>>>>> case X86II::MRMDestReg: { >>>>>>>> EmitByte(BaseOpcode, CurByte, OS); >...

...f (MO.isImmediate()) { > - emitConstant(MO.getImm(), sizeOfImm(Desc)); > + emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc)); > } else { > assert(0 && "Unknown RawFrm operand!"); > } > @@ -669,7 +534,7 @@ > > if (CurOp != NumOps) { > const MachineOperand &MO1 = MI.getOperand(CurOp++); > - unsigned Size = sizeOfImm(Desc); > + unsigned Size = X86InstrInfo::sizeOfImm(Desc); > if (MO1.isImmediate()) > emitConstant(MO1.getImm(), Size); > else { > @@ -698,7 +...

...t;>>>>>>>>> i made extensive use of gdb and after debugging i found the >>>>>>>>>> line with issue in X86MCCodeEmitter.cpp. >>>>>>>>>> >>>>>>>>>> Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. >>>>>>>>>> >>>>>>>>>> then, the following code gets executed; >>>>>>>>>> >>>>>>>>>> case X86II::MRMDestReg: { >>>>>>>>>>...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...E on X86 with SSE In X86InstrSSE.td, a MFENCE is def MFENCE : I<0xAE, MRM6m, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< [HasSSE2]>; In X86CodeEmitter.cpp in emitInstruction case X86II::MRM6m: case X86II::MRM7m: { intptr_t PCAdj = (CurOp+4 != NumOps) ? (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm (Desc) : 4) : 0; ... If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so we to get the 4th operand from the MFENCE operation which has no operands so we get an error. I'm not sure what...

...t;>>> i made extensive use of gdb and after debugging i found the >>>>>>>>>>>> line with issue in X86MCCodeEmitter.cpp. >>>>>>>>>>>> >>>>>>>>>>>> Here NumOps=3 (all registers). and CurOp is 1st initialized to >>>>>>>>>>>> 0. >>>>>>>>>>>> >>>>>>>>>>>> then, the following code gets executed; >>>>>>>>>>>> >>>>>>>>>&g...

...td, a MFENCE is > def MFENCE : I<0xAE, MRM6m, (outs), (ins), > "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< > [HasSSE2]>; > > In X86CodeEmitter.cpp in emitInstruction > > case X86II::MRM6m: case X86II::MRM7m: { > intptr_t PCAdj = (CurOp+4 != NumOps) ? > (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm > (Desc) : 4) : 0; > ... > > If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so > we to get the 4th operand from the MFENCE operation which has no > operands so we get an er...

...MFENCE : I<0xAE, MRM6m, (outs), (ins), >> "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< >> [HasSSE2]>; >> >> In X86CodeEmitter.cpp in emitInstruction >> >> case X86II::MRM6m: case X86II::MRM7m: { >> intptr_t PCAdj = (CurOp+4 != NumOps) ? >> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm >> (Desc) : 4) : 0; >> ... >> >> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so >> we to get the 4th operand from the MFENCE operation which has no >&gt...

...gt; #include <asm/edd.h> #include <asm/mtrr.h> #include "cpu/mtrr/mtrr.h" @@ -55,6 +55,7 @@ static long cpu_frequency_change_helper( ret_t do_platform_op(XEN_GUEST_HANDLE(xen_platform_op_t) u_xenpf_op) { ret_t ret = 0; + struct vcpu *v; struct xen_platform_op curop, *op = &curop; if ( !IS_PRIV(current->domain) ) @@ -312,7 +313,6 @@ ret_t do_platform_op(XEN_GUEST_HANDLE(xe { uint32_t cpu; uint64_t idletime, now = NOW(); - struct vcpu *v; struct xenctl_cpumap ctlmap; cpumask_t cpumap; XEN_GU...

...spin_lock(&d->event_lock); diff -r b9721b2766c1 xen/common/domctl.c --- a/xen/common/domctl.c Wed Jan 07 11:25:00 2009 +0000 +++ b/xen/common/domctl.c Thu Jan 08 18:58:36 2009 +0900 @@ -193,14 +193,49 @@ long do_domctl(XEN_GUEST_HANDLE(xen_domc long ret = 0; struct xen_domctl curop, *op = &curop; - if ( !IS_PRIV(current->domain) ) - return -EPERM; - if ( copy_from_guest(op, u_domctl, 1) ) return -EFAULT; if ( op->interface_version != XEN_DOMCTL_INTERFACE_VERSION ) return -EACCES; + + switch ( op->cmd ) + { + case...

I don't think changing to VEX_4VOp3 to VEX_4V is the right fix. I think the fix is to increment CurOp twice at the start for these instructions so that only the input operands are used for encoding. Also, I just submitted a patch to revert the operand order for these instructions in the assembler/disassembler. Destination register should appear on the right and the mask should appear on the left a...

Yes, there is an easy way to fix this. MRMSrcMem assumes register, memory, vvvv register if VEX_4VOp3 is true and assumes register, vvvv register, memory if VEX_4V is true. I just need to change the flag from VEX_4VOp3 to VEX_4V. There are a few places where we assume only the 2nd operand can be tied-to: Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1 (hard-coded index 1) I will fix those

...errno $5 = 1 Any ideas how to get this working, or on where I could get better diagnostics ? I''m guessing this is caused by this code in arch/x86/platform_hypercall.c : ret_t do_platform_op(XEN_GUEST_HANDLE(xen_platform_op_t) u_xenpf_op) { ret_t ret = 0; struct xen_platform_op curop, *op = &curop; if ( !IS_PRIV(current->domain) ) return -EPERM; So how do I make the IS_PRIV macro return non-zero for my domain_0 , ie. set d->is_privileged / make my domain0 into a "privileged" domain ? What is meant by "privileged" in this context ? Th...

Hi all, this patch series makes the necessary changes to make sure that the current ARM hypercall ABI can be used as-is on 64 bit ARM platforms: - it defines xen_ulong_t as uint64_t on ARM; - it introduces a new macro to handle guest pointers, called XEN_GUEST_HANDLE_PARAM (that has size 4 bytes on aarch and is going to have size 8 bytes on aarch64); - it replaces all the occurrences of

Hi all, this patch series makes the necessary changes to make sure that the current ARM hypercall ABI can be used as-is on 64 bit ARM platforms: - it defines xen_ulong_t as uint64_t on ARM; - it introduces a new macro to handle guest pointers, called XEN_GUEST_HANDLE_PARAM (that has size 4 bytes on aarch and is going to have size 8 bytes on aarch64); - it replaces all the occurrences of

These two patches were originally part of the XSM series that I have posted, and remain prerequisites for that series. However, they are independent of the XSM changes and are a useful simplification regardless of the use of XSM. The Acked-bys on these patches were provided before rebasing them over the copyback changes in 26268:1b72138bddda, which had minor conflicts that I resolved. [PATCH