llvm dev - Oct 2006 - [LLVMdev] Questions about instruction selection and instruction definitions

> On Wed, 4 Oct 2006, Roman Levenstein wrote:
> >> You can add the line
> >> setOperationAction(ISD::SELECT, MVT::i32, Expand);
> >> to the constructor of you TargetLowering class. See the current
> >> backend for an example.
> >
> > I actually tried it first. But then if, I remember correctly,
> SELECT
> > nodes were expanded into something using SELECT_CC, which is also
> not
> > supported on my target. Basically, only conditional branches are
> > supported. Therefore I thought about using the LowerSelect pass.
> But
> > I'll try again this evening. May be I was doing something wrong.
> >
> > What should be the result of expanding SELECT?  Some sort of
> > IF-THEN-ELSE flow?
> 
> Check out how the sparc or powerpc backends handle this.  They lower
> to a 
> select_cc pseudo-op that expands to an if/then/else control flow.
Thanks! The hint about a pseudo-op was really good. After I realized
how it works, I started the implementation of SELECT_CC using this
approach. Hopefully, I can finish it today.

Chris, may be you could provide some feedback about other questions
from the original mail? In particular about the register classes and
subclasses and about restrictions related to multiclasses? I'd be very
grateful.

-Roman 
  

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On Thu, 5 Oct 2006, Roman Levenstein wrote:
>> Check out how the sparc or powerpc backends handle this.  They lower
>> to a
>> select_cc pseudo-op that expands to an if/then/else control flow.
>
> Thanks! The hint about a pseudo-op was really good. After I realized how 
> it works, I started the implementation of SELECT_CC using this approach. 
> Hopefully, I can finish it today.
Great.
> Chris, may be you could provide some feedback about other questions
> from the original mail? In particular about the register classes and
> subclasses and about restrictions related to multiclasses? I'd be very
> grateful.
Can you resend it?  I apparently didn't get it or deleted it or something. 
I just saw the response to it.  Thanks,

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/

Hi,

What does it mean if a custom Node in the instructions description file
is declared to have a Chain? 
Looking at different backends, I have the impression that it describes
some sort of side effect and usually used for nodes affecting the
control flow. But I'm not quite sure. Can someone describe the
semantics of this property and also what is a typical usage of it?

In particular, I have found that CMP nodes for different targets are
described differently with regard to this property. ARM backend defines
armcmp without this property. PCC defines PCCvcmp and PCCvcmp_o also
without this property. In Sparc backend SPcmpicc is also not using it.
But X86cmp does for some reason. I'm trying to understand if I need it
for my backend or not.

It would be also interesting to get some information about other SDNP-*
SelectionDAG node properties, e.g. SDNPOutFlag, SDNPInFlag,
SDNPOptInFlag and their purpose.

-Roman

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