Displaying 4 results from an estimated 4 matches for "x86cmp".
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x86_mc
2013 May 20
2
[LLVMdev] VCOMISS instruction in X86
Hi,
I'm looking at scalar and packed instructions in X86.
The instruction VCOMISS is scalar. May I remove SSEPackedSingle/SSEPackedDouble domain from it?
defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, TB, OpSize, VEX,...
2006 Oct 05
1
[LLVMdev] The meaning of SDNPHasChain
...usage of it?
In particular, I have found that CMP nodes for different targets are
described differently with regard to this property. ARM backend defines
armcmp without this property. PCC defines PCCvcmp and PCCvcmp_o also
without this property. In Sparc backend SPcmpicc is also not using it.
But X86cmp does for some reason. I'm trying to understand if I need it
for my backend or not.
It would be also interesting to get some information about other SDNP-*
SelectionDAG node properties, e.g. SDNPOutFlag, SDNPInFlag,
SDNPOptInFlag and their purpose.
-Roman
_____________________________________...
2006 Oct 05
0
[LLVMdev] Questions about instruction selection and instruction definitions
On Thu, 5 Oct 2006, Roman Levenstein wrote:
>> Check out how the sparc or powerpc backends handle this. They lower
>> to a
>> select_cc pseudo-op that expands to an if/then/else control flow.
>
> Thanks! The hint about a pseudo-op was really good. After I realized how
> it works, I started the implementation of SELECT_CC using this approach.
> Hopefully, I can
2006 Oct 05
2
[LLVMdev] Questions about instruction selection and instruction definitions
> On Wed, 4 Oct 2006, Roman Levenstein wrote:
> >> You can add the line
> >> setOperationAction(ISD::SELECT, MVT::i32, Expand);
> >> to the constructor of you TargetLowering class. See the current
> >> backend for an example.
> >
> > I actually tried it first. But then if, I remember correctly,
> SELECT
> > nodes were expanded into