search for: spcmpicc

...property and also what is a typical usage of it? In particular, I have found that CMP nodes for different targets are described differently with regard to this property. ARM backend defines armcmp without this property. PCC defines PCCvcmp and PCCvcmp_o also without this property. In Sparc backend SPcmpicc is also not using it. But X86cmp does for some reason. I'm trying to understand if I need it for my backend or not. It would be also interesting to get some information about other SDNP-* SelectionDAG node properties, e.g. SDNPOutFlag, SDNPInFlag, SDNPOptInFlag and their purpose. -Roman ____...

On Thu, 5 Oct 2006, Roman Levenstein wrote: >> Check out how the sparc or powerpc backends handle this. They lower >> to a >> select_cc pseudo-op that expands to an if/then/else control flow. > > Thanks! The hint about a pseudo-op was really good. After I realized how > it works, I started the implementation of SELECT_CC using this approach. > Hopefully, I can

> On Wed, 4 Oct 2006, Roman Levenstein wrote: > >> You can add the line > >> setOperationAction(ISD::SELECT, MVT::i32, Expand); > >> to the constructor of you TargetLowering class. See the current > >> backend for an example. > > > > I actually tried it first. But then if, I remember correctly, > SELECT > > nodes were expanded into

...defm ADDCC : F3_12<"addcc", 0b010000, addc>; defm ADDX : F3_12<"addx" , 0b001000, adde>; defm SUB : F3_12<"sub" , 0b000100, sub>; defm SUBX : F3_12<"subx" , 0b001100, sube>; defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>; ... Each of these 'defm's expand into two instructions. > The semantic of such a description would mean that $dst should be one > of GR8, GR16, GR32 and $dst is one of i8mem, i16mem, i32mem with the > additional constraint that the sizes of both operands are the same > (t...

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

...<"addcc", 0b010000, addc>; > defm ADDX : F3_12<"addx" , 0b001000, adde>; > defm SUB : F3_12<"sub" , 0b000100, sub>; > defm SUBX : F3_12<"subx" , 0b001100, sube>; > defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>; > ... > > Each of these 'defm's expand into two instructions. > >> The semantic of such a description would mean that $dst should be one >> of GR8, GR16, GR32 and $dst is one of i8mem, i16mem, i32mem with the >> additional constraint that the sizes of bo...

...* --- 154,162 ---- def SDTSPtlsld : SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; + def SDTSPeh_sjlj_setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>; + def SDTSPeh_sjlj_longjmp: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; + def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; *************** *** 172,177 **** --- 175,187 --...