search for: select_cc

Eli, Thanks for the tips. I've been able to get something working using a custom instruction inserter, however, I'm still having the problem of linking together the setcc and the select_cc commands. I want to turn the setcc into a comparison and use the results in the select_cc register. However, the comparison information is in the select_cc instruction and the result of the comparison is in the setcc instruction. What I am trying to figure out is using MachineInstruction/MachineBas...

Can someone explain how the condition code is passed from the MBlazeTargetLowering::LowerSELECT_CC to MBlazeTargetLowering::EmitCustomSelect custom inserter? In LowerSELECT_CC the condition code is never accessed (Op.GetOperand(4)) and I don't see how it ends up getting correctly passed to the MBlazeTargetLowering::EmitCustomSelect. > SDValue MBlazeTargetLowering::LowerSELECT_CC(SDVa...

Hello, I'd like to write some unit tests which verifies SELECT_CC and BR_CC lowering for ARM target, but I'm almost completely unfamiliar with llvm/Target. How can I get this nodes in DAG? Thanks. -- Kind regards, Dmitry Borisenkov -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-d...

...; I am attempting to lower the selectCC instruction to the instruction set of > the backend I'm working on and I cannot seem to find a way to correctly > implement this instruction. I know how this instruction should get > implemented; I just have yet to find a way to do it. I want the select_cc > instruction to be lowered into a comparison followed by a conditional move. "setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);" should do the trick; that will prevent SELECT_CC instructions from being introduced. This one is easy to miss. > def CMOVLOG : InstF...

Hi All, I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END; mov rX,0; END:" sequence. Chris mentioned that the PPC code (as well as the x86 SSE code) does this, but I can't seem to find it. What I really need to kmow is how to insert the branch/label pair at instruction selection phase. Anyone have an e...

I am attempting to lower the selectCC instruction to the instruction set of the backend I'm working on and I cannot seem to find a way to correctly implement this instruction. I know how this instruction should get implemented; I just have yet to find a way to do it. I want the select_cc instruction to be lowered into a comparison followed by a conditional move. I've attempted to use a custom rule pasted below, but it keeps giving me an error about the first argument. What I attempted is as follows: class InstFormat<dag outs, dag ins, string asmstr, list<dag> patter...

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction...

someguy wrote: > Hi All, > > I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END; > mov rX,0; END:" sequence. > > Chris mentioned that the PPC code (as well as the x86 SSE code) does > this, but I can't seem to find it. > > What I really need to kmow is how to insert the branch/label pair at > instruction s...

...ration phase. The initially generated code is shown as follows (as a pseudo code): ( Before pseudo-code expansion. ) ---------- loop: : : set P0 <- xxx ( P0: a physical register for a parameter of function F ) set P1 <- yyy ( P1: a physical register for a parameter of function F ) SELECT_CC z1, z2, z3, ... ( <- I don't know why this is scheduled at this time, however it is independent from function F ) call F : : ---------- After that, pseudo code expansion stage expands SELECT_CC by slicing the machine basic clock. ---------- loop: : : set P0 &l...

...= regTrue 2) either condition2 = !condition In this case, regTrue is a phi node between the initial value of result and the current result. In this case, the sequence of 3 instructions cannot be reduced easily ! So, my question is (finally ;)): Is there a way to introduce some intelligence in the select_cc lowering by reversing the condition if it is likely to generate more efficient code ? I am asking this question because the lowering works on basic blocks with a set of input virtual registers and output virtual registers and all the connections between these 2 set of registers seemed to be "l...

...s shown as follows (as a pseudo code): > ( Before pseudo-code expansion. ) > > ---------- > loop: > : > : > set P0 <- xxx ( P0: a physical register for a parameter of function F ) > set P1 <- yyy ( P1: a physical register for a parameter of function F ) > SELECT_CC z1, z2, z3, ... > ( <- I don't know why this is scheduled at this time, > however it is independent from function F ) > call F > : > : > ---------- > > After that, pseudo code expansion stage expands SELECT_CC by slicing the machine basic cloc...

Hi Rafael, > I am trying to add support for select_cc. In ARM it can be implemented > with: > > mov $dst, $falseVal > cmp $a, $b > moveq $dst, $trueVal The more normal ARM code, as produced by assembly writers and compilers that I've seen, is cmp $a, $b moveq $dst, $trueVal movne $dst, $falseVal e.g. at the end of a f...

On Mon, Aug 21, 2006 at 05:09:10PM -0300, Rafael Espíndola wrote: > I am trying to add support for select_cc. In ARM it can be implemented > with: [snip] Speaking of new backends, there is a document that lists some architecture docs: http://llvm.org/docs/CompilerWriterInfo.html . There is a link to the GCC library as well, which is rather extensive and may be helpful in writing a new backend. If yo...

...ke some advice. Here's what is happening: On PPC32 VAARG is custom lowered (in PPCTargetLowering::LowerVAARG) and can create two ISD::SELECT nodes that use a ISD::SETCC node with a ISD::SETLT parameter. On PPC, ISD::SELECT is expanded, and here both of these SELECT nodes are expanded into ISD::SELECT_CC nodes with a ISD::SETLT node used by both. These SELECT_CC nodes are not directly instruction selected, instead they should be handled by the PPCDAGToDAGISel::Select function. This function always transforms SELECT_CC nodes into PPC-specific nodes that can be instruction selected; in doing so the...

> If you find any good references to optimization manuals, etc. that > aren't mentioned there, please send them along. In http://www.arm.com/products/DevTools/ABI.html there is a collection of documents regarding the ABI for the ARM architecture. Best Regards, Rafael

...the line >> setOperationAction(ISD::SELECT, MVT::i32, Expand); >> to the constructor of you TargetLowering class. See the current >> backend for an example. > > I actually tried it first. But then if, I remember correctly, SELECT > nodes were expanded into something using SELECT_CC, which is also not > supported on my target. Basically, only conditional branches are > supported. Therefore I thought about using the LowerSelect pass. But > I'll try again this evening. May be I was doing something wrong. > > What should be the result of expanding SELECT? Some...

...Action(ISD::SELECT, MVT::i32, Expand); > >> to the constructor of you TargetLowering class. See the current > >> backend for an example. > > > > I actually tried it first. But then if, I remember correctly, > SELECT > > nodes were expanded into something using SELECT_CC, which is also > not > > supported on my target. Basically, only conditional branches are > > supported. Therefore I thought about using the LowerSelect pass. > But > > I'll try again this evening. May be I was doing something wrong. > > > > What should be th...

...his way? > You can add the line > setOperationAction(ISD::SELECT, MVT::i32, Expand); > to the constructor of you TargetLowering class. See the current > backend for an example. I actually tried it first. But then if, I remember correctly, SELECT nodes were expanded into something using SELECT_CC, which is also not supported on my target. Basically, only conditional branches are supported. Therefore I thought about using the LowerSelect pass. But I'll try again this evening. May be I was doing something wrong. What should be the result of expanding SELECT? Some sort of IF-THEN-ELSE f...

What guarantees, if any, does the scheduler make when two selection nodes are linked by a Flag type? Can I expect the machine instructions that are selected from the two nodes to be scheduled consecutively? I'm trying to implement code generation for SELECT_CC nodes in a back end that I'm working on. The compare operations on the architecture communicate via bits in a global status register, much like on MSP430. In fact, I've modeled my implementation after that of the MSP430. So I have custom target nodes akin to MSP430cmp and MSP430selectcc and...

...::Other, Expand); setOperationAction(ISD::SETCC, MVT::i32, Expand); setOperationAction(ISD::SETCC, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); I sort of have an intuition what it is doing, but quite nail it.Do you mind explaining it? Also I didn't add any of the setOperationAction for the MVT::v4i32 and my simple test case worked. How come?...