Hello Axel,
I'm an undergraduate student who has been working on a student project
implementing a project like this for our Fourth Year Design Symposium
(http://eceprojects.uwaterloo.ca
).
Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I
think that much of this would hold for your students project as well.
The project took significantly longer to complete than we had
originally anticipated. We have recently completed our hardware
implementation after having spent approximately 5 months after classes
to complete the project (The project was taken in addition to our
normal course load of 4 courses). We estimate that it was
approximately 2000 man hours of work to complete our reference
implementation.
If your students are good with time management, and are well versed in
RTL design, I would imagine it could be done with less time.
Coincidentally, we are presenting our project tomorrow at the design
symposium, and giving a talk on the project. If you would like to
learn more about our project, I encourage you to check out our website:
http://hquad.project.googlepages.com
, which links to our publications and design documents. Also, I would
be happy to answer any other questions you may have.
Regards,
Cole Stewart
4B Computer Engineering
University of Waterloo
On 22-Jan-08, at 3:00 PM, flac-dev-request@xiph.org wrote:
> Hello,
>
> my name is Axel Reimer and I am new to this mailing list. I subscribed
> because I was just thinking about how hard it would be to implement a
> flac-decoder in VHDL (in order to use it on a Xilinx-FPGA).
>
> Since I am working at a University in Germany I was thinking of
> offering
> this project for students.
>
> What do you think. How much time would you suggest for such an
> implementation (if only one students with VHDL knowledge works on it)
> and where is a good point to start?
>
> Best regards,
>
> Axel
