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Hello Axel, I'm an undergraduate student who has been working on a student project implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca ). Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I think that much of this would hold for your students project as well. The project took significantly longer to complete than we had originally anticipated. We have recently completed our hardware imple...

...l documented format and such helpful mailing lists. For background on the project, you can check out our project website: http://hquad.project.googlepages.com/ or contact us at our team mailing list: hquad.project@gmail.com You can find out more about the design project symposium below: http://eceprojects.uwaterloo.ca/symposium.html The demo will take place on Wednesday, January 23rd, from 9am-8pm. If anyone is in the area and interested in attending, the event is open to the public. The symposium takes place in the University of Waterloo's Davis Centre. University of Waterloo 200 Uni...