search for: vhdl

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a descripti...

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a desc...

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (...

Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL support, but if I implement at least entities/architectures, concurrent statem...

To All,     Has anyone worked with generating vhdl code to promela script for the spin model checker??   David Blubaugh         -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121204/b76bd607/attachment.html>

...; > You can reach the person managing the list at > flac-dev-owner@xiph.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of Flac-dev digest..." > > > Today's Topics: > > 1. Implementing a flac-decoder in VHDL (Axel Reimer) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 22 Jan 2008 13:26:16 +0100 > From: Axel Reimer <mailinglists@fpgas.de> > Subject: [Flac-dev] Implementing a flac-decoder in VHDL > To: flac-dev@xip...

Thanks for your answers. In one year, I am going to have something like a semester project. The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL support, but if I implement at least entities/architectures, concurrent statem...

I don't have a solution for you, but when you found one or start the project on your own, let me know. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111002/f54dd8de/attachment.html>

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only one students with VHDL knowledge works on it) and where is a good point...

Hello Axel, I'm an undergraduate student who has been working on a student project implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca ). Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I think that much of this would hold for your students project as well. The project took significantly longer to complete than we had originally anticipated. We have recently completed our hardware implementation after having spent...

...ke phatnoise which is software based). The car will support both playback and archival. There will be a wireless (802.11a?) link between both servers which will sync when in range. I found this link: http://www.celoxica.com/home.htm They have a C to (V)HDL converter. I'm just now learning VHDL and was wondering if anyone has tried to implement it yet. If so I would like to see your code for reference/starting point. Thanks in advance Alijah Ballard

Hi Pavel, > If you are interested in HDLs perhaps you would be interested in Vlang? > I am currently working on Verilog fronted and I am looking for somebody with > VHDL interest to join the Vlang project. I have never heard about the Vlang project but it seems to be an interesting project. I think I could be interested to join this project and do the VHDL front-end. However, there are some points that you should be aware : * I have never joined an open-source pro...

...his transformation... not sure exactly what you need. I need to get rid of phis. This code is compiled from C++ and for some functions there are no phis, but multiple call instructions. I am targeting hardware in the end, and the next tool reading the IR does not like phis when it's generating VHDL. My questions may be somewhat silly from the viewpoint of software compilation for a CPU. Thanks. Teemu

...s working on a local disk. Other users did not experience any problem on this machine so it was only one sub-directory (and everything below). I checked the syslog both on the client and on the server, but no messages of interest. [root at arend ~]# stat /home/stbo/workarea/toekan/design/dig/vhdl/fpga/fpga_top.vhd File: `/home/stbo/workarea/toekan/design/dig/vhdl/fpga/fpga_top.vhd' Size: 53214 Blocks: 112 IO Block: 4096 regular file Device: fd01h/64769d Inode: 6614395 Links: 1 Access: (0664/-rw-rw-r--) Uid: ( 635/ stbo) Gid: ( 635/ stbo) Access:...

...eason for that? Or is it only because it seems not to be useful for llc? I want to use it in an backend that is derived from the CBackend. I need the information what functions are called in every other function to build communication struktures between the functions. The backend is generating VHDL from C code. (VHDL is a hardware description language, which means it is used to generate hardware, for those who are not familiar with this.) I've managed to compile my backend with the CallGraph pass, but when it try to use it, I get an error, which I could't fix until now. llc --lo...

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLV...

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support than Fortran 77 and C89. David On 30 Aug 2013, at 10:43, Jonas Baggett <jonasb at tranquille.ch...

Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not :-) . An...

Hey! I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0? active-HDL (i regret to say) is only for windows.... :( Thanks :)

...6. Re: replacing a global variable by a constant (neda 8664) 7. Re: replacing a global variable by a constant (Duncan Sands) 8. Re: VLIW Ports (Carlos S?nchez de La Lama) 9. Re: svnsync of llvm tree (Oliver Schneider) 10. Re: svnsync of llvm tree (Oliver Schneider) 11. TR : LLVM and VHDL simulation (Baggett Jonas) 12. Re: TableGen and Greenspun (David A. Greene) 13. Re: svnsync of llvm tree (David A. Greene) 14. Re: svnsync of llvm tree (Jeff Fifield) 15. Re: LLVM and VHDL simulation (Jianzhou Zhao) 16. Re: TableGen and Greenspun (David A. Greene) 17. How to create argu...