similar to: Re: Implementing a flac-decoder in VHDL

I'd like to announce the first public demo of a hardware FLAC decoder that I and three of my colleagues have been working on over the past 8 months. This project has been developed as part of the University of Waterloo's Fourth Year Design Project requirement for undergrad students in Electrical & Computer Engineering. Our decoder has been implemented in VHDL and is currently

Quoting flac-dev-request@xiph.org: > Send Flac-dev mailing list submissions to > flac-dev@xiph.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.xiph.org/mailman/listinfo/flac-dev > or, via email, send a message with subject or body 'help' to > flac-dev-request@xiph.org > > You can reach the person managing the list at >

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This

Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm

Thanks for your answers. In one year, I am going to have something like a semester project. The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL

Hi Pavel, > If you are interested in HDLs perhaps you would be interested in Vlang? > I am currently working on Verilog fronted and I am looking for somebody with > VHDL interest to join the Vlang project. I have never heard about the Vlang project but it seems to be an interesting project. I think I could be interested to join this project and do the VHDL front-end. However, there are

Today a user asked me whether a file on one host can be different on another host. I was busy composing an answer to tell that the /home space on all clients are mounted using NFS from the file server. Any host will therefor see the same file. The user pointed me to his file and I copied this file from the client and compared this with the file on the file server. To my surprise it turned out

To All,     Has anyone worked with generating vhdl code to promela script for the spin model checker??   David Blubaugh         -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121204/b76bd607/attachment.html>

I'm currently looking to start my working on my major project for College. I want to create an audio CD archival/ playback server. There will be a base server and also several satellite players. I will be building a secondary server for my car. And in the car power is at a premium so I wanted true hardware support (unlike phatnoise which is software based). The car will support both

Dear R users, my search for a possibility to convert a generated model into VHDL to program an FPGA has still no solution. The problem: caret -> training -> model -> model.rds -> model.xml (PMML) --?--> VHDL-Code --?--> FPGA The (simplified) task: A photo detector with 16 channels is measuring the intensity of 16 different wavelength ranges. These data are classified with the

Hi, I am sending my application I submitted for the GSoC. There are still some hours left before the deadline, so if you have any remarks or a tip, I can still update it. thanks... i think there are some grammatical errors =(... == Name and Contact details == Andr? Luiz Nazareth da Costa Primary e-mail: andre.lnc@gmail.com Secondary e-mail: andre.lnc@lsc.ic.unicamp.br Gtalk:

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations,

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the

I don't have a solution for you, but when you found one or start the project on your own, let me know. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111002/f54dd8de/attachment.html>

A simulator should be expecting the machine opcodes not macros. LD shouldn't care at all as long as the object format plays well. I would think it would be better to fix the simulator. Jack ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of llvmdev-request at cs.uiuc.edu [llvmdev-request at cs.uiuc.edu] Sent: Thursday,

Seth, Thank you for your reply. I'm sorry to bother with this, but what is the "root pivot" function and where can I find doc's on it. From what I understand from your email the system would basically boot twice. Once from a stripped kernel on the floppy disk to mount the CD, and then after the CD is mounted it would reboot with the kernel and initial randisk found on the

Hi, I suspect a CPU bottleneck in one of our PostgreSQL servers but not sure how to confirm the suspect. It's a DELL Box running CentOS 5.4 with 64GB RAM and 16 XEON E7430 2.13 GHz processors. vmstat r column "run queue" usually indicates values higher than 2 and less than 5 but "Load Average" values from top, sar -q and other commands show always values less than 1.