search for: fpga

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased...

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased...

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the decoder (as Ben pointed out), but a good...

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the hardware modul...

Hi, We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps. What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation? Best regards Fredrik Bonde -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/opus/attachments/20131004/e72bbd53/attachment.htm

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware with Xilinx "CHiMPS" interface for FPGA but probably CHiMPS doesn't have any freely available eval version of CHiMPS to try with LLVM for study purposes. I 'op...

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially im...

...y <nicholas at mxc.ca> wrote: > The way in which Gallium3D targets LLVM, is that it waits until it receives > the shader program from the application, then compiles that down to LLVM IR. > That's too late to start synthesizing hardware (unless you're planning to > ship an FPGA as the graphics card, in which case reprogramming is still too > slow, and it'll be too expensive). nick.... the Zynq-7000 series of Dual-Core Cortex A9 800mhz 28nm CPUs have an on-board Series 7 Artix-7 or Kinect-7 FPGA (depending on the Zynq range). and that's on the same silicon IC...

Good day! I create diagram of encoder process. Using it i create implementation of encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing stages? Here is blog http://developer-fpga.blogspot.com/ Here is picture of encoding stage 1 https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg Here is picture of encoding stage 2 https://lh5.goog...

....ca> wrote: > >> The way in which Gallium3D targets LLVM, is that it waits until it receives >> the shader program from the application, then compiles that down to LLVM IR. >> That's too late to start synthesizing hardware (unless you're planning to >> ship an FPGA as the graphics card, in which case reprogramming is still too >> slow, and it'll be too expensive). > > nick.... the Zynq-7000 series of Dual-Core Cortex A9 800mhz 28nm CPUs > have an on-board Series 7 Artix-7 or Kinect-7 FPGA (depending on the > Zynq range). and that'...

Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The...

Andrey Fillipov posted the following update at his sourceforge website on 11/16/04. "Coded and simulated the DC predictor module - hope the Theora description I used matches the actual codec :-) Also modified the modules released earlier to support non-coded blocks. For the DCT/IDCT I tried to reduce the power consuption by minimizing switching of the registers and counters when the

...would be as equally simple (the only FSF Hardware-Endorsed > laptop product is that Loongson Leemote, by virtue of it having a 2D > PCI Graphics IC and a 900mhz MIPS). > > the logic goes as follows: > * one of the Gallium3D targets is LLVM. > * one of LLVM's targets is Xilinx FPGAs (MicroBlaze). > * the zynq-7000 7030 has 125k FPGA Logic Gates (and more) > * with a TFP410 as the DVI driver, the OGP is done! > > now, given that this appears to be "too easy", i'd really _really_ > appreciate some help checking the facts. and, also, if it turns out...

...ith decent 3D Graphics Engine would be as equally simple (the only FSF Hardware-Endorsed laptop product is that Loongson Leemote, by virtue of it having a 2D PCI Graphics IC and a 900mhz MIPS). the logic goes as follows: * one of the Gallium3D targets is LLVM. * one of LLVM's targets is Xilinx FPGAs (MicroBlaze). * the zynq-7000 7030 has 125k FPGA Logic Gates (and more) * with a TFP410 as the DVI driver, the OGP is done! now, given that this appears to be "too easy", i'd really _really_ appreciate some help checking the facts. and, also, if it turns out to be feasible, assessi...

Dear R users, my search for a possibility to convert a generated model into VHDL to program an FPGA has still no solution. The problem: caret -> training -> model -> model.rds -> model.xml (PMML) --?--> VHDL-Code --?--> FPGA The (simplified) task: A photo detector with 16 channels is measuring the intensity of 16 different wavelength ranges. These data are classified with the...

I'm not aware of an FPGA implementations yet. You could be the first! An encoder implementation would be much easier, because there are almost no rules about encoders. An encoder is free to behave any way it wants, so you could implement a very small subset of Opus and still have a compliant (and useful) encoder. A dec...

Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

...est at xiph.org > > You can reach the person managing the list at > theora-dev-owner at xiph.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of theora-dev digest..." > > > Today's Topics: > > 1. FPGA encode stages flow diagram (digital design) > 2. Re: FPGA encode stages flow diagram (Timothy B. Terriberry) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 22 Mar 2011 20:42:59 +0300 > From: digital design <devel...

Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the output. 2. Corresponding 6 blocks from the previous frame are fetched from the same FB in para...