klibc - Apr 2015 - [PATCH] mips: setjmp: allow working with fpxx/fp64 abi

This patch is needed to allow klibc to be compiled on a mips compiler configured
to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU
registers cannot be used directly, but they can be accessed using the double
word sdc1 and ldc1 instructions.

See this page for more info:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Signed-off-by: James Cowgill <james410 at cowgill.org.uk>
---
 usr/klibc/arch/mips/setjmp.S | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/usr/klibc/arch/mips/setjmp.S b/usr/klibc/arch/mips/setjmp.S
index 68eed19..c6963c4 100644
--- a/usr/klibc/arch/mips/setjmp.S
+++ b/usr/klibc/arch/mips/setjmp.S
@@ -29,6 +29,14 @@ LEAF(setjmp)
 	sw	s8, 40(a0)
 	sw	ra, 44(a0)
 	cfc1	t0,$31
+#if __mips_fpr == 0 || __mips_fpr == 64
+	sdc1	$f20,48(a0)
+	sdc1	$f22,56(a0)
+	sdc1	$f24,64(a0)
+	sdc1	$f26,72(a0)
+	sdc1	$f28,80(a0)
+	sdc1	$f30,88(a0)
+#else
 	swc1	$f20,48(a0)
 	swc1	$f21,52(a0)
 	swc1	$f22,56(a0)
@@ -41,6 +49,7 @@ LEAF(setjmp)
 	swc1	$f29,84(a0)
 	swc1	$f30,88(a0)
 	swc1	$f31,92(a0)
+#endif
 	sw	t0,96(a0)
 	move	v0,zero
 	jr	ra
@@ -61,6 +70,14 @@ LEAF(longjmp)
 	lw	s8, 40(a0)
 	lw	ra, 44(a0)
 	lw	t0, 96(a0)
+#if __mips_fpr == 0 || __mips_fpr == 64
+	ldc1	$f20,48(a0)
+	ldc1	$f22,56(a0)
+	ldc1	$f24,64(a0)
+	ldc1	$f26,72(a0)
+	ldc1	$f28,80(a0)
+	ldc1	$f30,88(a0)
+#else
 	lwc1	$f20,48(a0)
 	lwc1	$f21,52(a0)
 	lwc1	$f22,56(a0)
@@ -73,6 +90,7 @@ LEAF(longjmp)
 	lwc1	$f29,84(a0)
 	lwc1	$f30,88(a0)
 	lwc1	$f31,92(a0)
+#endif
 	ctc1	t0,$31
 	move	v0,a1
 	jr	ra
-- 
2.1.4