search for: fpxx

...32-bit registers). At the moment, this extension is available in all the tools and is enabled with -mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code since they require the FPU to be in different modes. To fix the compatibility flaw, we are adding an O32 extension called fpxx (enabled with -mfpxx) which operates correctly in both FPU modes and is essentially O32 with some minor restrictions. O32+fpxx is ABI-compatible with O32 and O32+fp64 and can inter-link with either but not both at the same time (because they conflict with eachother). The intention is that as code i...

This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgil...

James Cowgill dixit: >klibc does this when it saves all the FPU registers in its setjmp Hm, shouldn?t klibc not use the FPU at all? AFAIK it was unsupported to use it. bye, //mirabilos -- <hecker> cool ein Ada Lovelace Google-Doodle. aber zum 197. Geburtstag? H?tten die nicht noch 3 Jahre warten k?nnen? <mirabilos> bis dahin gibts google nicht mehr <hecker> ja, k?nnte man

...y, each step is ABI compatible with the previous step. The linker will ensure that the end-user doesn't try to do the second step before the first step is finished since it will refuse to link a binary that contains both O32 and O32+fp64. It will produce an O32 binary given a combination of O32+fpxx, and similarly a O32+fp64 binary given a combination O32+fpxx and O32+fp64. > Interesting. I'd seen some of the discussion, but not read it in any detail. >> Curious why an extension to o32 for this and not, for example, just using n32? > > N32 is an ABI that requires 64-bit ge...

...some > source files > > > > > Warning: float register should be even, was 7 > > Could you add –save-temps to the compiler command and send me the > command along with the .i and .s file the compiler produces? > > This warning is usually related to something called FPXX. FPXX is an > extension to the O32 ABI that causes the compiler to generate objects > that can be used on both a 32-bit and 64-bit FPU. In recent compilers > it is enabled by default. The most likely cause of the warning is some > inline assembly that doesn't obey the small rest...

On 06/12/2015 07:12 PM, Daniel Sanders wrote: > > Hi, > > I'm afraid targeting a 64-bit CPU and the O32 ABI is completely broken > at the moment, it's one of the very long-standing issues I'm working > towards. The main problem is that a lot of the internals of the Mips > LLVM backend derive their behaviour from the target CPU rather than > the target ABI.

On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with

Klibc FTBFS with '-mno-odd-spreg' on mips32(el) platforms, As it try to save/restore odd-number FPR. Indeed no other architectures save/restore FPR at all. It shouldn't be needed. --- usr/klibc/arch/mips/setjmp.S | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/usr/klibc/arch/mips/setjmp.S b/usr/klibc/arch/mips/setjmp.S index 68eed19..21e4115 100644 ---

Any idea about it? It may be a serious problem, as some distributions are using FPXX by default. On Sat, Sep 5, 2015 at 9:39 PM, YunQiang Su <wzssyqa at gmail.com> wrote: > Klibc FTBFS with '-mno-odd-spreg' on mips32(el) platforms, > As it try to save/restore odd-number FPR. > > Indeed no other architectures save/restore FPR at all. > It shouldn't...

...Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips: don't save floating point registers in setjmp / longjmp Don't bother saving any floating point registers in setjmp or restoring them in longjmp. This causes issues when compiling for the FPXX ABI, and is unnessesary as klibc does not support floating point code. Additionally, remove the unused parts of __jmp_buf. Signed-off-by: James Cowgill <james.cowgill at mips.com> Link: https://www.zytor.com/pipermail/klibc/2018-March/003983.html Signed-off-by: Ben Hutchings <ben at decad...

...ame thing but with a clear separation between the parser and the target description. > > Various details (ELF headers, label prefixes, exception personality, JIT target, etc.) depend on the ABI and OS Distribution rather than just 32-bit vs 64-bit > Sure? Yep. Some OS Distributions have FPXX enabled by default. Likewise for NAN2008 (although this is currently rare). Some (will) permit mixing IEEE754-1985 and IEEE754-2008 NAN encodings (they aren't the same on Mips due to historical choices). This ends up in the ELF headers. It's related to the second class of issues discussed b...

Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library

...ach will have wildly different ABIs. For 1) When I run gcc I get n64+softfloat+nan2008+i6400 For 2) When I run gcc I get n32+hardfloat+doublefloat+nan2008+i6400 For 1) when I run gcc -mabi=32 I get o32+soft-float+nan2008+i6400 For 2) when I run gcc -mabi=32 I get o32+hardfloat+doublefloat+nan2008+fpxx+i6400 If I want to use clang as simply as I use GCC what do I need to change in llvm/clang to create a compiler such that I can replace ‘gcc’ above with ‘clang’ and get the same effect? Thanks, Matthew From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Eric Christopher via l...

Hi Daniel, > (from the context, you might have meant 'tuple' where you've written > 'triple'. I'm answering based on the assumption you meant 'triple') > > I did mean what I wrote. > The GNU triple is already used as a way of encoding a large amount of the > target data in a string but unfortunately, while this data is passed > throughout

Hi Eric, Thanks for getting back to me on this. > I'm not sure I agree with the basic idea of using the target triple as a way of > encoding all of the pieces of target data as a string. I think in a number of > cases what we need to do is either open up API to the back end to specify things, > or encode the information into the IR when it's different from the generic triple.

...;ve seen MIPS-II, MIPS32, MIPS32R2. They can't all be the one true meaning. * I've also seen one instance of it meaning little endian. * Modern toolchains will mean NAN2008, existing ones usually mean NAN1985. (IEEE754-2008 made MIPS's QNaN/SNaN encodings wrong) * Some use O32 FPXX instead of plain O32 FP32. * The sysroot layout for mips-mti-linux-gnu significantly changed in recent toolchains. We can't hardcode both layouts since they're mutually exclusive and very different. * Likewise for mips-img-linux-gnu toolchains. * mips-linux-gnu -mips64 should produce...

I think we need to take a step further back and re-enter from the right starting point. The thing that's bothering me about the push back so far is that it's trying to discuss and understand the consequences of resolving the core problem while seemingly ignoring the core problem itself. The reason I've been steering everything back to GNU Triple's being ambiguous and inconsistent

> OK, I'm going to just reply to the last because I think it's the most important part of all this and would like to try to have us side tracked again. If you'd like I can reply to it, but let's take the last part first :) > > > > Could you please provide some examples of things that are impossible right now > > > with command lines, how those interact with