search for: swc1

Displaying 13 results from an estimated 13 matches for "swc1".

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2015 Sep 05
3
[PATCH] mips/setjmp.S don't save and restore float point registers
...------------ 1 file changed, 24 deletions(-) diff --git a/usr/klibc/arch/mips/setjmp.S b/usr/klibc/arch/mips/setjmp.S index 68eed19..21e4115 100644 --- a/usr/klibc/arch/mips/setjmp.S +++ b/usr/klibc/arch/mips/setjmp.S @@ -29,18 +29,6 @@ LEAF(setjmp) sw s8, 40(a0) sw ra, 44(a0) cfc1 t0,$31 - swc1 $f20,48(a0) - swc1 $f21,52(a0) - swc1 $f22,56(a0) - swc1 $f23,60(a0) - swc1 $f24,64(a0) - swc1 $f25,68(a0) - swc1 $f26,72(a0) - swc1 $f27,76(a0) - swc1 $f28,80(a0) - swc1 $f29,84(a0) - swc1 $f30,88(a0) - swc1 $f31,92(a0) sw t0,96(a0) move v0,zero jr ra @@ -61,18 +49,6 @@ LEAF(longjmp) lw s8...
2015 Sep 09
0
[PATCH] mips/setjmp.S don't save and restore float point registers
...ps/setjmp.S b/usr/klibc/arch/mips/setjmp.S > index 68eed19..21e4115 100644 > --- a/usr/klibc/arch/mips/setjmp.S > +++ b/usr/klibc/arch/mips/setjmp.S > @@ -29,18 +29,6 @@ LEAF(setjmp) > sw s8, 40(a0) > sw ra, 44(a0) > cfc1 t0,$31 > - swc1 $f20,48(a0) > - swc1 $f21,52(a0) > - swc1 $f22,56(a0) > - swc1 $f23,60(a0) > - swc1 $f24,64(a0) > - swc1 $f25,68(a0) > - swc1 $f26,72(a0) > - swc1 $f27,76(a0) > - swc1 $f28,80(a0) > - swc1...
2019 Jan 18
0
[klibc:master] mips: don't save floating point registers in setjmp / longjmp
...ps/setjmp.S index 68eed19..9145dbc 100644 --- a/usr/klibc/arch/mips/setjmp.S +++ b/usr/klibc/arch/mips/setjmp.S @@ -9,8 +9,6 @@ # sp # s8 # ra -# f20..f31 -# fcr31 # #include <machine/asm.h> @@ -28,20 +26,6 @@ LEAF(setjmp) sw sp, 36(a0) sw s8, 40(a0) sw ra, 44(a0) - cfc1 t0,$31 - swc1 $f20,48(a0) - swc1 $f21,52(a0) - swc1 $f22,56(a0) - swc1 $f23,60(a0) - swc1 $f24,64(a0) - swc1 $f25,68(a0) - swc1 $f26,72(a0) - swc1 $f27,76(a0) - swc1 $f28,80(a0) - swc1 $f29,84(a0) - swc1 $f30,88(a0) - swc1 $f31,92(a0) - sw t0,96(a0) move v0,zero jr ra @@ -60,20 +44,6 @@ LEAF(longjmp) lw...
2015 Apr 23
0
[PATCH] mips: setjmp: allow working with fpxx/fp64 abi
...ibc/arch/mips/setjmp.S +++ b/usr/klibc/arch/mips/setjmp.S @@ -29,6 +29,14 @@ LEAF(setjmp) sw s8, 40(a0) sw ra, 44(a0) cfc1 t0,$31 +#if __mips_fpr == 0 || __mips_fpr == 64 + sdc1 $f20,48(a0) + sdc1 $f22,56(a0) + sdc1 $f24,64(a0) + sdc1 $f26,72(a0) + sdc1 $f28,80(a0) + sdc1 $f30,88(a0) +#else swc1 $f20,48(a0) swc1 $f21,52(a0) swc1 $f22,56(a0) @@ -41,6 +49,7 @@ LEAF(setjmp) swc1 $f29,84(a0) swc1 $f30,88(a0) swc1 $f31,92(a0) +#endif sw t0,96(a0) move v0,zero jr ra @@ -61,6 +70,14 @@ LEAF(longjmp) lw s8, 40(a0) lw ra, 44(a0) lw t0, 96(a0) +#if __mips_fpr == 0 || __mips_fpr...
2018 Mar 02
5
[PATCH 0/5] Various MIPS fixes
Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library
2014 Mar 11
4
[PATCH] add mips64 support
...+# sp +# s8 +# ra +# f20..f31 +# fcr31 +# + +#include <machine/asm.h> + +LEAF(setjmp) + sw s0, 0(a0) + sw s1, 4(a0) + sw s2, 8(a0) + sw s3, 12(a0) + sw s4, 16(a0) + sw s5, 20(a0) + sw s6, 24(a0) + sw s7, 28(a0) + sw gp, 32(a0) + sw sp, 36(a0) + sw s8, 40(a0) + sw ra, 44(a0) + cfc1 t0,$31 + swc1 $f20,48(a0) + swc1 $f21,52(a0) + swc1 $f22,56(a0) + swc1 $f23,60(a0) + swc1 $f24,64(a0) + swc1 $f25,68(a0) + swc1 $f26,72(a0) + swc1 $f27,76(a0) + swc1 $f28,80(a0) + swc1 $f29,84(a0) + swc1 $f30,88(a0) + swc1 $f31,92(a0) + sw t0,96(a0) + move v0,zero + jr ra + + END(setjmp) + +LEAF(longjmp) + lw s0...
2017 Dec 31
4
[PATCH klibc 0/4] Fixes from Debian and Ubuntu
The following patches come from Debian and/or Ubuntu packages of klibc. Ben. Ben Hutchings (1): [klibc] run-init: Add dry-run mode Jay Vosburgh (1): [klibc] ipconfig: Use separate sockets for DHCP from multiple interfaces Mathieu Trudel-Lapierre (1): [klibc] ipconfig: Set broadcast when sending DHCPREQUEST and DHCPDISCOVER YunQiang Su (1): [klibc] mips: setjmp.S: don't
2006 Jun 26
2
[klibc 28/43] mips support for klibc
...+# sp +# s8 +# ra +# f20..f31 +# fcr31 +# + +#include <machine/asm.h> + +LEAF(setjmp) + sw s0, 0(a0) + sw s1, 4(a0) + sw s2, 8(a0) + sw s3, 12(a0) + sw s4, 16(a0) + sw s5, 20(a0) + sw s6, 24(a0) + sw s7, 28(a0) + sw gp, 32(a0) + sw sp, 36(a0) + sw s8, 40(a0) + sw ra, 44(a0) + cfc1 t0,$31 + swc1 $f20,48(a0) + swc1 $f21,52(a0) + swc1 $f22,56(a0) + swc1 $f23,60(a0) + swc1 $f24,64(a0) + swc1 $f25,68(a0) + swc1 $f26,72(a0) + swc1 $f27,76(a0) + swc1 $f28,80(a0) + swc1 $f29,84(a0) + swc1 $f30,88(a0) + swc1 $f31,92(a0) + sw t0,96(a0) + move v0,zero + jr ra + + END(setjmp) + +LEAF(longjmp) + lw s0...
2014 Jun 23
2
[LLVMdev] Is there any tool can generate MIPS ELF file?
...conflict with eachother). The intention is that as code is re-compiled, O32+fpxx will replace O32 and we will end up the mode requirements being either 'FR=1' or "don't care". > > In case you're curious, the fpxx restrictions are: > * Use of mtc1, mfc1, lwc1, and swc1 on the upper 32-bits of a double precision value is not permitted. > * Some callee-saved registers are also treated as caller-saved. > Well, this is definitely ABI breaking, so effectively a new ABI is what I meant. Curious why an extension to o32 for this and not, for example, just using n...
2014 Jun 08
2
[LLVMdev] [llvm] r210424 - Revert "Do materialize for floating point"
...7,9 @@ bool MipsFastISel::EmitStore(MVT VT, uns > // > // more cases will be handled here in following patches. > // > - if (VT == MVT::i32) > - EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); > - else if (VT == MVT::f32) > - EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset); > - else if (VT == MVT::f64) > - EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset); > - else > + if (VT != MVT::i32) > return false; > + EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); > return true...
2014 Jun 24
2
[LLVMdev] Is there any tool can generate MIPS ELF file?
...hat as code is re-compiled, >> O32+fpxx will replace O32 and we will end up the mode requirements being >> either 'FR=1' or "don't care". >> > >> > In case you're curious, the fpxx restrictions are: >> > * Use of mtc1, mfc1, lwc1, and swc1 on the upper 32-bits of a double >> precision value is not permitted. >> > * Some callee-saved registers are also treated as caller-saved. >> > >> >> Well, this is definitely ABI breaking, so effectively a new ABI is what I >> meant. >> >> Curio...
2014 Jun 18
2
[LLVMdev] Is there any tool can generate MIPS ELF file?
On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with
2006 Jun 28
35
[klibc 00/31] klibc as a historyless patchset (updated and reorganized)
I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: