search for: fp64

...in_nanl("")' is returning the value 0x0000000000000000. I tested this builtin with our v4.0 compiler and it has the same problem, so this is not a regression but rather an existing bug exposed by the new LibC++ implementation of '<limits>'. But our implementation of FP64 is a software only implementation using the FP64 support functions in 'compiler-rt' and we have no lowering actions of our own. Where should I be looking to find out how to fix this? Is it a CLang issue of an LLVM issue? Thanks, MartinO -------------- next part...

Most of codegen is already FP64-ready. There are a few edge-cases that I ran into, many of which can apply even to non-fp64-enabled programs (although the double-wide registers are not very common without fp64). I've yet to give this a full piglit run, but wanted to send these out in case someone wanted to comment. They do n...

...“”)’ is returning the > value 0x0000000000000000.  I tested this builtin with our v4.0 > compiler and it has the same problem, so this is not a regression but > rather an existing bug exposed by the new LibC++ implementation of > ‘<limits>’. > > But our implementation of FP64 is a software only implementation using > the FP64 support functions in ‘compiler-rt’ and we have no lowering > actions of our own. > > Where should I be looking to find out how to fix this?  Is it a CLang > issue of an LLVM issue? > __builtin_nanl("") gets constant-...

This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgill

Hi All, This series implements using double immediates in the nouveau codegen code. This turns the following (nvc0) code: 1: mov u32 $r2 0x00000000 (8) 2: mov u32 $r3 0x3fe00000 (8) 3: add f64 $r0d $r0d $r2d (8) Into: 1: add f64 $r0d $r0d 0.500000 (8) This has been tested with the 2 double shader tests which I just send to the piglet list. On a gk208 (gk110 / SM35)

...Node->getOperand(0).getValueType()); break; case ISD::EXTRACT_VECTOR_ELT: Action = TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType()); Is this assumption correct? I cannot get LLVM to expand fp64 -> i64 nodes into either to a custom lowered function or expanded to a software function call. Is getConvertAction being removed? If so, how should I handle this in the backend? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm...

Hi Hans, All pushed. I made a few additional fixes and improvement to fp64 immediate handling along the way, but all your commits were fine as-is. (Except that they enabled fp64 immediates on nv50 implicitly which is wrong -- there are no immediate-taking variants on nv50, so I fixed that glitch. But only the G200 can do fp64 in the first place, and nouveau doesn't ac...

...supported extension that allows the efficient use of FR=1 mode (FPU with 64-bit registers). This is going to be important since MIPS32r6/MIPS64r6 will not have direct support for FR=0 mode (FPU with 32-bit registers). At the moment, this extension is available in all the tools and is enabled with -mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code since they require the FPU to be in different modes. To fix the compatibility flaw, we are adding an O32 extension called fpxx (enabled with -mfpxx) which operates correctly in both FPU modes and is essentially O32 with some min...

...).getValueType()); > break; > case ISD::EXTRACT_VECTOR_ELT: > Action = TLI.getOperationAction(Node->getOpcode(), > Node->getOperand(0).getValueType()); > > > > Is this assumption correct? I cannot get LLVM to expand fp64 -> i64 nodes into either to a custom lowered function or expanded to a software function call. > > > Is getConvertAction being removed? If so, how should I handle this in the backend? With the current code, FP_TO_SINT and FP_TO_UINT go to the default case, which looks up getOperati...

...e it. > > For the time being, I'd suggest defining an "fp register set" which > just aliases the integer register set (i.e. say that d0 overlaps > r0+r1). OK. I almost did this way already. But I introduced two FP register sets. One for fp32 (for the future) and one for fp64. fp32 aliases the integer register set. fp64 aliases the fp32 register set, but not the integer register set explicitly. I thought that aliases are transitive? Or do I have to mention all aliases explicitly, e.g. for %d0 I need to say [%s0,%s1,%GR0,%GR1]? But a more interesting question is this: T...

...the time being, I'd suggest defining an "fp register set" which >> just aliases the integer register set (i.e. say that d0 overlaps >> r0+r1). > > OK. I almost did this way already. But I introduced two FP register > sets. One for fp32 (for the future) and one for fp64. fp32 aliases the > integer register set. fp64 aliases the fp32 register set, but not the > integer register set explicitly. I thought that aliases are transitive? > Or do I have to mention all aliases explicitly, e.g. for %d0 I need to > say [%s0,%s1,%GR0,%GR1]? Depending on how you d...

...don't want an extra layer of abstraction (which adds extra looking-ups to someone reading td files), but I think we can have for-loop inside a multiclass without abstractions. -------------------- multiclass sse_binop<opcode> { for type = [f32, f64, v4f32, v2f64] regclass = [FP32, FP64, VR128, VR128] suffix = [ss, sd, ps, pd] { def !toupper(suffix)#rr : Instr< [(set (type regclass:$dst), (type (opcode (type regclass:$src1), (type regclass:$src2))))]>; def !toupper(suffix)#rm : Instr< [(set (type regclas...

> So in summary, each step is ABI compatible with the previous step. The linker will ensure that the end-user doesn't try to do the second step before the first step is finished since it will refuse to link a binary that contains both O32 and O32+fp64. It will produce an O32 binary given a combination of O32+fpxx, and similarly a O32+fp64 binary given a combination O32+fpxx and O32+fp64. > Interesting. I'd seen some of the discussion, but not read it in any detail. >> Curious why an extension to o32 for this and not, for example,...

On Mon, 9 Oct 2006, Roman Levenstein wrote: > I'm now ready to implement the FP support for my embedded target. cool. > My target supports only f64 at the moment. > Question: How can I tell LLVM that float is the same as double on my > target? May be by assigning the same register class to both MVT::f32 > and MVT::f64? Just don't assign a register class for the f32 type.

...abstraction (which > adds extra looking-ups to someone reading td files), but I think we > can have for-loop inside a multiclass without abstractions. > > -------------------- > multiclass sse_binop<opcode> { > for type = [f32, f64, v4f32, v2f64] > regclass = [FP32, FP64, VR128, VR128] > suffix = [ss, sd, ps, pd] { > > def !toupper(suffix)#rr : Instr< > [(set (type regclass:$dst), (type (opcode (type regclass:$src1), > (type regclass:$src2))))]>; > def !toupper(suffix)#rm : Instr<...

Hi, I'm now ready to implement the FP support for my embedded target. My target supports only f64 at the moment. Question: How can I tell LLVM that float is the same as double on my target? May be by assigning the same register class to both MVT::f32 and MVT::f64? But FP is supported only in the emulated mode, because the target does not have any hardware support for FP. Therefore each FP

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested beyond compiling a few shaders to see if they look like they might work. nvdisasm agrees with envydis's decoding of these things. Will definitely get ahold of a G200 to run tests on before pushing this. .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 94 ++++++++++++++++++---

...} report is just a function that prints the results. in main the assemply code seems to be ok but in test2 function does something that seems to be wrong i use "llc -march=mipsel -relocation-model=static -asm-verbose -mattr=+condmov,-muldivadd,+single-float,-fp64,+o32,-bitcount " command in function we report the values of a long long value then an integer value and then again a long long so the problem is that in the test2 function there is an addiu $3, $2, 4 that causes the third long long value to be read from wrong address. mipsel.s...

On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with

...express this? Using the for-loop syntax: // WARNING: Pseudo-code, many details elided for presentation purposes. multiclass binop<opcode> : sse_binop<opcode>, avx_binop<opcode>; multiclass sse_binop<opcode> { for type = [f32, f64, v4f32, v2f64] regclass = [FP32, FP64, VR128, VR128] suffix = [ss, sd, ps, pd] { def !toupper(suffix)#rr : Instr< [(set (type regclass:$dst), (type (opcode (type regclass:$src1), (type regclass:$src2))))]>; def !toupper(suffix)#rm : Instr< [(set (type r...