search for: ldc1

Displaying 13 results from an estimated 13 matches for "ldc1".

Did you mean: dc1
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 BB#0: derived from LLVM BB %entry SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 The first two stores write the values in argument registers $6 and $7 to frame object -1 (Mips stores byval arguments passed in registers to the stack). The fourth instruction LDC1 loads the value written by the first two stores as a floating point dou...
2012 Mar 07
0
[LLVMdev] Question about post RA scheduler
...A3 in %vreg2 > > BB#0: derived from LLVM BB %entry > SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 > SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 > %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 > %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 > > > The first two stores write the values in argument registers $6 and $7 > to frame object -1 > (Mips stores byval arguments passed in registers to the stack). > The fourth instruction LDC1 loads the value written by the first two...
2015 Apr 23
0
[PATCH] mips: setjmp: allow working with fpxx/fp64 abi
This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgill <james410 at cowgill.org.uk> --- usr/klibc/arch/mips/setjmp.S | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/usr/klibc/a...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...d from LLVM BB %entry >>       SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>       SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>       %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>       %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >> >> >> The first two stores write the values in argument registers $6 and $7 >> to frame object -1 >> (Mips stores byval arguments passed in registers to the stack). >> The fourth instruction LDC1 loads the value wri...
2012 Mar 13
0
[LLVMdev] Question about post RA scheduler
...entry >>> SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >>> >>> >>> The first two stores write the values in argument registers $6 and $7 >>> to frame object -1 >>> (Mips stores byval arguments passed in registers to the stack). >>> The fourth instructio...
2018 Jul 16
2
Need advice on upgrading from 4.3.11 to 4.8.3
...Rowland I tried to join 4.8.2 (latest one at Louis Van Belle's repo) but I got this error: ----------------- ldc4# samba-tool domain join testdomain.org.tr DC -U"TESTDOMAIN\administrator" --dns-backend=BIND9_DLZ Finding a writeable DC for domain 'testdomain.org.tr' Found DC ldc1.testdomain.org.tr Password for [TESTDOMAIN\administrator]: workgroup is TESTDOMAIN realm is testdomain.org.tr Adding CN=LDC4,OU=Domain Controllers,DC=testdomain,DC=org,DC=tr Join failed - cleaning up ERROR(ldb): uncaught exception - LDAP error 68 LDAP_ENTRY_ALREADY_EXISTS -  <00002071: ../ldb_td...
2012 Mar 15
2
[LLVMdev] Question about post RA scheduler
...t;>       SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>>>       SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>>>       %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>>>       %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >>>> >>>> >>>> The first two stores write the values in argument registers $6 and $7 >>>> to frame object -1 >>>> (Mips stores byval arguments passed in registers to the stack). >>>>...
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
...mpilationCallbackC\n" "nop\n" // Restore registers. - "lw $a0, 20($sp)\n" - "lw $a1, 24($sp)\n" - "lw $a2, 28($sp)\n" - "lw $a3, 32($sp)\n" - "lw $ra, 36($sp)\n" - "lw $t8, 40($sp)\n" - "ldc1 $f12, 48($sp)\n" - "ldc1 $f14, 56($sp)\n" - "addiu $sp, $sp, 64\n" + "lw $4, 20($29)\n" + "lw $5, 24($29)\n" + "lw $6, 28($29)\n" + "lw $7, 32($29)\n" + "lw $31, 36($29)\n" + "lw $24, 40($29)\n&q...
2018 Jul 16
0
Need advice on upgrading from 4.3.11 to 4.8.3
...test one at Louis Van Belle's repo) but I > got this error: > > ----------------- > ldc4# samba-tool domain join testdomain.org.tr DC > -U"TESTDOMAIN\administrator" --dns-backend=BIND9_DLZ Finding a > writeable DC for domain 'testdomain.org.tr' Found DC > ldc1.testdomain.org.tr Password for [TESTDOMAIN\administrator]: > workgroup is TESTDOMAIN > realm is testdomain.org.tr > Adding CN=LDC4,OU=Domain Controllers,DC=testdomain,DC=org,DC=tr > Join failed - cleaning up > ERROR(ldb): uncaught exception - LDAP error 68 > LDAP_ENTRY_ALREADY_EXI...
2018 Jul 15
5
Need advice on upgrading from 4.3.11 to 4.8.3
Hi all, We have a Samba AD DC service running on Ubuntu 16.0.4 with Samba 4.3.11. We are planning to upgrade it to a recent version, probably 4.8.3. I think that I have two options: a) Package upgrade via 3rd party repositories (Louis Van Belle's repo) by following wiki. b) A fresh install of 4.8.3 on another VM then join it to 4.3.11 as backup DC, then transfer all FSMO roles on new and
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248 4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use> 4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243 45...
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The
2014 Jun 23
2
[LLVMdev] Is there any tool can generate MIPS ELF file?
On Mon, Jun 23, 2014 at 2:45 AM, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: >> There are a lot of MIPS ABIs. > > Yes, and we've discovered that there seem to be incompatible extensions to some of these ABI's too. :) > >> I'm pretty sure Imagination Technologies working up a new abi right now. > > Not exactly. We're not working on any