search for: _fr0_and_fr1_interlinking

...compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgill <james410 at cowgill.org.uk> --- usr/klibc/arch/mips/setjmp.S | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/usr/klibc/arch/mips/setjmp.S b/usr/klibc/arch/mips/setjmp.S index 68eed19..c6963c4 100644 --- a/usr/klibc/arch/mips/setjmp.S +++...