I'm having a great deal of trouble figuring out how to write instruction patterns which actually match the DAG produced by the compiler. I can't seem to find any documentation on both what the various nodes represent or on what the syntax accepted by TableGen is. The backends I have access to all seem to do this in different (and obscure) ways. And when things go wrong the compiler seems to dump the DAG tree in a entirely different syntax to that used by TableGen. Can anyone point me at any decent resources as to what all this stuff actually does? And how to figure out what's going wrong when it inevitably does go wrong? So far all I've found is include/llvm/Target/TargetSelectionDAG.td, which at least lists them but doesn't say what they do, and the C++ implementations in SelectionDAGNodes.h, which is entirely undocumented... -- ┌─── dg@cowlark.com ───── http://www.cowlark.com ───── │ │ "You cannot truly appreciate _Atlas Shrugged_ until you have read it │ in the original Klingon." --- Sea Wasp on r.a.sf.w -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 876 bytes Desc: OpenPGP digital signature URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140308/1ce78333/attachment.sig>
On Mar 7, 2014, at 4:28 PM, David Given <dg at cowlark.com> wrote:> Can anyone point me at any decent resources as to what all this stuff > actually does? And how to figure out what's going wrong when it > inevitably does go wrong? > > So far all I've found is include/llvm/Target/TargetSelectionDAG.td, > which at least lists them but doesn't say what they do, and the C++ > implementations in SelectionDAGNodes.h, which is entirely undocumented...Generally speaking, the Graphviz options (such as -view-isel-dags) to visualize DAGs are your friends. ISDOpcodes.h contains what documentation there is on the semantics of each opcode. —Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140307/ee9fcaa7/attachment.html>
On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote:> ISDOpcodes.h contains what documentation there is on the semantics of each > opcode.And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in MachineInstr form, but you'll see them with -view-sched-dags, and occasionally before). Tim.
You can use -mllvm -debug-only=isel to see the DAG during the lowering process, and it will look mostly like what you see in the error messages. You can also add statements that print the SD nodes to the code that builds the DAG, or the DAG combiner. I'd take a working backend, and watch what happens when I modify the .td files. Pick one that seems the easiest to understand, or simply ask about the obscurity when something looks strange. Your experiences with this are probably not uncommon... -Krzysztof On 3/7/2014 6:28 PM, David Given wrote:> I'm having a great deal of trouble figuring out how to write instruction > patterns which actually match the DAG produced by the compiler. I can't > seem to find any documentation on both what the various nodes represent > or on what the syntax accepted by TableGen is. The backends I have > access to all seem to do this in different (and obscure) ways. And when > things go wrong the compiler seems to dump the DAG tree in a entirely > different syntax to that used by TableGen. > > Can anyone point me at any decent resources as to what all this stuff > actually does? And how to figure out what's going wrong when it > inevitably does go wrong? > > So far all I've found is include/llvm/Target/TargetSelectionDAG.td, > which at least lists them but doesn't say what they do, and the C++ > implementations in SelectionDAGNodes.h, which is entirely undocumented... > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Seemingly Similar Threads
- [LLVMdev] Isel DAG documentation?
- [LLVMdev] Type inference on registers with can contain multiple types
- [LLVMdev] Isel DAG documentation?
- [LLVMdev] Partially complete LLVM backend for the VideoCore 4
- [LLVMdev] Question about porting LLVM - code selection without assembler feature