David Given
2014-Mar-19 23:18 UTC
[LLVMdev] Type inference on registers with can contain multiple types
My architecture has an FPU, but uses integer registers to store
floating-point values. So each register can store either an int or an
IEEE float. I define a register class like this:
def GR32 : RegisterClass<"MyArch", [i32, f32], 32,
(sequence "R%u", 0, 32)>;
So far so good. However, when I write a rule to store a register:
def STORE32r : S32<
(outs), (ins GR32:$rS, GR32:$rD),
"st {$rS, ($rD)}",
[(store GR32:$rS, (iPTR GR32:$rD))]>;
...then I get the dreaded 'cannot infer all types in pattern' error.
This is presumably because tablegen can't tell whether the input is an
i32 or a f32.
What's the best thing to do here? Explicitly annotating the input type
works, of course, but then I need two rules. Use a multipattern? Or is
there a way to tell tablegen that the input is allowed to be either?
--
┌─── ｄｇ＠ｃｏｗｌａｒｋ．ｃｏｍ ───── http://www.cowlark.com ─────
│
│ "You cannot truly appreciate _Atlas Shrugged_ until you have read it
│ in the original Klingon." --- Sea Wasp on r.a.sf.w
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Hal Finkel
2014-Mar-19 23:41 UTC
[LLVMdev] Type inference on registers with can contain multiple types
----- Original Message -----> From: "David Given" <dg at cowlark.com> > To: "LLVM Dev" <llvmdev at cs.uiuc.edu> > Sent: Wednesday, March 19, 2014 6:18:53 PM > Subject: [LLVMdev] Type inference on registers with can contain multiple types > > My architecture has an FPU, but uses integer registers to store > floating-point values. So each register can store either an int or an > IEEE float. I define a register class like this: > > def GR32 : RegisterClass<"MyArch", [i32, f32], 32, > (sequence "R%u", 0, 32)>; > > So far so good. However, when I write a rule to store a register: > > def STORE32r : S32< > (outs), (ins GR32:$rS, GR32:$rD), > "st {$rS, ($rD)}", > [(store GR32:$rS, (iPTR GR32:$rD))]>; > > ...then I get the dreaded 'cannot infer all types in pattern' error. > This is presumably because tablegen can't tell whether the input is > an > i32 or a f32. > > What's the best thing to do here? Explicitly annotating the input > type > works, of course, but then I need two rules. Use a multipattern? Or > is > there a way to tell tablegen that the input is allowed to be either?You'll need to write the pattern with a single type. In your *ISelLowering.cpp, can you mark the store of the other type as Promote, and then promote it to the type for which there is a pattern? As I recall, the PowerPC backend does this for its vector types. -Hal> > -- > ┌─── ｄｇ＠ｃｏｗｌａｒｋ．ｃｏｍ ───── http://www.cowlark.com ───── > │ > │ "You cannot truly appreciate _Atlas Shrugged_ until you have read > it > │ in the original Klingon." --- Sea Wasp on r.a.sf.w > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Hal Finkel Assistant Computational Scientist Leadership Computing Facility Argonne National Laboratory
Tom Stellard
2014-Mar-20 13:27 UTC
[LLVMdev] Type inference on registers with can contain multiple types
On Wed, Mar 19, 2014 at 06:41:02PM -0500, Hal Finkel wrote:> ----- Original Message ----- > > From: "David Given" <dg at cowlark.com> > > To: "LLVM Dev" <llvmdev at cs.uiuc.edu> > > Sent: Wednesday, March 19, 2014 6:18:53 PM > > Subject: [LLVMdev] Type inference on registers with can contain multiple types > > > > My architecture has an FPU, but uses integer registers to store > > floating-point values. So each register can store either an int or an > > IEEE float. I define a register class like this: > > > > def GR32 : RegisterClass<"MyArch", [i32, f32], 32, > > (sequence "R%u", 0, 32)>; > > > > So far so good. However, when I write a rule to store a register: > > > > def STORE32r : S32< > > (outs), (ins GR32:$rS, GR32:$rD), > > "st {$rS, ($rD)}", > > [(store GR32:$rS, (iPTR GR32:$rD))]>; > > > > ...then I get the dreaded 'cannot infer all types in pattern' error. > > This is presumably because tablegen can't tell whether the input is > > an > > i32 or a f32. > > > > What's the best thing to do here? Explicitly annotating the input > > type > > works, of course, but then I need two rules. Use a multipattern? Or > > is > > there a way to tell tablegen that the input is allowed to be either? > > You'll need to write the pattern with a single type. In your *ISelLowering.cpp, can you mark the store of the other type as Promote, and then promote it to the type for which there is a pattern? As I recall, the PowerPC backend does this for its vector types. >This is what R600 does as well. All floating-point loads/stores are promoted to integer and then we just have integer load/store patterns. -Tom> > > > -- > > ┌─── ｄｇ＠ｃｏｗｌａｒｋ．ｃｏｍ ───── http://www.cowlark.com ───── > > │ > > │ "You cannot truly appreciate _Atlas Shrugged_ until you have read > > it > > │ in the original Klingon." --- Sea Wasp on r.a.sf.w > > > > > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > > -- > Hal Finkel > Assistant Computational Scientist > Leadership Computing Facility > Argonne National Laboratory > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev