search for: targetselectiondag

...entheses. Where does predicate fit in this picture? I don't see any mention of predicates in lang ref manual. A DAG should have an operator, one or more return value and a bunch of arguments. Each of them would have a type. I am not sure how that maps to syntax provided by TableGen language. In TargetSelectionDAG.td I see (vt SDNode) in definition of ImmLeaf. Does that mean vt is return type of SDNode? 2. Entity followed after "(" is always need to be an operator? or it can be ValueType or something else? 3. What are keywords like "ins", "outs" and "ops"? They are no...

...de fragments (you'd think this'd already be in // a > td > >> file somewhere... :-) > > > > And this comment makes me think, shouldn't this class CodeFrag be > > included in the same place where PatFrag is declared: > > > > ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag > ops, > > dag frag, code pred = [{}], > > > > such that we get it included through "llvm/Target/Target.td"? > > > > I will prepare a patch for this. > > > > Please see the attached patch. Ok to commit? > >...

...ion logic just looks for the pattern `(set > GPR:$rd, (add GPR:$rA, GPR:$rB))`. It then becomes a simple substitution. > This is a DAG because there all nodes are directed and acyclic. > Am I correct in my understanding that each node can either be a register or of type SDNode defined in TargetSelectionDAG.td? > On Thu, Jan 28, 2016 at 7:33 PM, Rail Shafigulin via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> I'm confused about how to specify DAG patterns for a given instruction >> >> Here is an example for my target >> >> class ALU1_RR<bit...

...e to add a test case? I am not really sure what I would check. At first, I thought to add a testcase to test/TableGen; as this patch does not modify tablegen, it doesn't make sense. What kind of test should I write for this? The test should be a tablegen file that includes "llvm/Target/TargetSelectionDAG.td" or "llvm/Target/Target.td", and I haven't seen any of these in the testsuite. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

...is using code and pattern fragments: > > // Holder of code fragments (you'd think this'd already be in > // a td file somewhere... :-) And this comment makes me think, shouldn't this class CodeFrag be included in the same place where PatFrag is declared: ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag ops, dag frag, code pred = [{}], such that we get it included through "llvm/Target/Target.td"? I will prepare a patch for this. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

The language I'm targeting doesn't have flags; I'd like to implement ADDE as a macro or psuedo-instruction that takes 3 parameters and returns 2. In my InstrInfo.td file, tablegen complains if I try to define multiple return values; adde is defined in TargetSelectionDAG.td to be a binary op that takes an extra flag in and sends an extra flag out. I tried to custom lower ADDE (by calling setOperationAction with ISD::ADDE) but it didn't seem to register and still bailed when trying to expand adde, instead of calling my LowerOperation. I could figure out...

Hello David, Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR instruction of "set" in "LLVM Language Reference Manual". Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is

...attern `(set >> GPR:$rd, (add GPR:$rA, GPR:$rB))`. It then becomes a simple substitution. >> This is a DAG because there all nodes are directed and acyclic. >> > > > Am I correct in my understanding that each node can either be a register > or of type SDNode defined in TargetSelectionDAG.td? > I should clarify. What I'm confused about is how exactly the DAG is defined. Here is what is says on llvm.org/docs/TableGen/LangIntro.html (DEF a, b)a dag value. The first element is required to be a record definition, the remaining elements in the list may be arbitrary other values,...

...seems to dump the DAG tree in a entirely different syntax to that used by TableGen. Can anyone point me at any decent resources as to what all this stuff actually does? And how to figure out what's going wrong when it inevitably does go wrong? So far all I've found is include/llvm/Target/TargetSelectionDAG.td, which at least lists them but doesn't say what they do, and the C++ implementations in SelectionDAGNodes.h, which is entirely undocumented... -- ┌─── ｄｇ＠ｃｏｗｌａｒｋ．ｃｏｍ ───── http://www.cowlark.com ───── │ │ "You cannot truly appreciate _Atlas Shrugged_ until you have read it │ in the or...

...: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also, why is it assumed that all comparison results are always integers? If I put GPRI32 as my destination register, it complains about register classes not matching...... Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great...

...] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like "set", "add", ... coming from include/llvm/Target/TargetSelectionDAG.td presumably these tokens are related to the enum in include/llvm/CodeGen/MachineValueType.h but how does tblgen know about them, To put the question into context, if I add an item to the enum in "MachineValueType.h" What do I do about "error: Var...

Hi, I was wondering if someone could explain precisely what the ComplexPattern tablegen class does? Here's the first line of the definition (from TargetSelectionDAG.td) for reference: class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = [], list<SDNodeProperty> props = [], list<CPAttribute> attrs = []> As far as I can tell it gives the name of...

This patch corrects the stated location of TargetSelectionDAG.td in the documentation and has a few spelling corrections in the comments and docs. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100323/04c0ffcf/attachment.html> -------------- next part --------------...

...: >> >> // Holder of code fragments (you'd think this'd already be in >> // a td file somewhere... :-) > > And this comment makes me think, shouldn't this class CodeFrag be > included in the same place where PatFrag is declared: > > ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag ops, > dag frag, code pred = [{}], > > such that we get it included through "llvm/Target/Target.td"? > > I will prepare a patch for this. > Please see the attached patch. Ok to commit? Thanks, Sebastian -- Qualcomm Innovation Center, Inc i...

I have an operation which loads a 16 bit block of data as 2 8-bit elements, sign extends the both parts to 32 bits and stores the result into 64-bit vector register. How can I define the pattern for this? just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] gives me error that extloav2i8 is not defined. (the same principle works for scalar sextload) So I need to define it

Hi Heikki, > just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] > > gives me error that extloav2i8 is not defined. I don't have a target to test this on, but looking at include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" PatFrag, at least. I'd suggest a pattern along the lines of: (set V2I32Regs:$result, (v2i32 (sextloadvi8 ADDRrr:$address))) Tim.

...rote: > The language I'm targeting doesn't have flags; I'd like to implement > ADDE as a macro or psuedo-instruction that takes 3 parameters and > returns 2. > > In my InstrInfo.td file, tablegen complains if I try to define > multiple return values; adde is defined in TargetSelectionDAG.td to be > a binary op that takes an extra flag in and sends an extra flag out. > > I tried to custom lower ADDE (by calling setOperationAction with > ISD::ADDE) but it didn't seem to register and still bailed when trying > to expand adde, instead of calling my LowerOperation. A...

...86ISD::INSERTPS is an extra instruction for ISel; it's used inside > the custom lowering for INSERT_VECTOR_ELT and VECTOR_SHUFFLE. Yes, that's how I found out about it. :) Why not just use ISD::INSERT_VECTOR_ELT? And what's the difference between vector_extract and extractelt in TargetSelectionDAG.td? Ditto vector_insert vs. insertelt. -Dave

...: Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, > GPRF32:$src1), “eq $dst, $src0, $src1”, [(set GPRF32:$dst, (seteq > GPRF32:$src0, GPRF32:$src1))]>; > > And it is failing stating that the result must be an integer. Is > there a way around this other than modifying TargetSelectionDAG.td? > Also, why is it assumed that all comparison results are always > integers? > If I put GPRI32 as my destination register, it complains about > register classes not matching…… > > > > Micah Villmow > Systems Engineer > Advanced Technology & Performance &g...

...r> <br> multiclass PTX_LOGIC_20P<string opcstr, PatFrag opnode> { ... }<br> <br> This will correctly match the opnode, though it'll depend on the other 2-operand logic instructions whether this is how it should be done. If you look at the definitions in include/Target/TargetSelectionDAG.td, you'll see which instructions are defined as a PatFrag and which are plain SDNodes.<br> <br> Dan<br> <br> <blockquote cite="mid:20110509013918.GA13760@cs.nctu.edu.tw" type="cite"> <pre wrap=""> But the error is still the s...