search for: dag

Displaying 20 results from an estimated 5386 matches for "dag".

2005 Dec 05
2
Re: [users] CentOS 4.2 dag repo problem.
Hello, It would be nice if we could get a full list of packages which have a wrong sha1 checksum. I don't have the bandwidth for a full mirror of all of Dag's rpms and i also don't have shell access to such a mirror. So a small request for a mirror admin: The following checks the files repodata/*.xml.gz against the sha1 sums in repomd.xml and checks the RPMS/*.rpm files against the sha1 sums in primary.xml.gz. Can you run this on the repod...
2009 Dec 01
4
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
...alizeIntegerTypes.cpp. Below is the original code and the proposed fix. Could someone please review the changes? If they are correct how do I go about submitting a patch? Thanks, Javier [Original] /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift /// of any size. bool DAGTypeLegalizer:: ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Amt = N->getOperand(1); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT ShTy = Amt.getValueType(); unsigned NVTBits = NVT.getSizeInBits(); assert(isPo...
2015 Dec 17
2
Deleting Public Mailbox?
Hi! What am I doing wrong here? Mission: Delete old empty sub mailboxes in our Public mailspace acl-file contents: MailingLists user=dag lrwstipekxa MailingLists/* user=dag lrwstipekxa Didn't work from my mail client so tried: Command tried: % doveadm mailbox delete -s MailingLists/Glibc -u dag doveadm(dag): Error: Can't delete mailbox MailingLists/Glibc: Permission denied % doveadm acl debug -u dag "M...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more complicated? Consider the case of an illegal operation (like division) on a <2 x...
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...an wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant >> >> simplification. There are still some issues with this patch, but >> does >> >> the approach look sane? Can you explain why you chose the approach of using a new pass? I pictured removing LegalizeDAG...
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: >> Can you explain why you chose the approach of using a new pass? >> I pictured removing LegalizeDAG's type legalization code would >> mostly consist of finding all the places that use TLI.getTypeAction >> and just deleting code for handling its Expand and Promote. Are you >> anticipating something more complicated? > > Consider the case of an illegal operation (like di...
2008 Sep 08
0
[LLVMdev] adde/addc
...edu/mailman/listinfo/llvmdev > I needed to do exactly the same for my target. I set ISD::ADD to be custom expanded (setOperationAction(ISD::ADD, MVT::i64, Custom)) and the same for ISD::SUB. I then added the following code to my target to do the expansion: ExpandADDSUB(SDNode *N, SelectionDAG &DAG) { assert(N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); // Extract components SDOperand LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConsta...
2009 Mar 30
2
[LLVMdev] RFC: X86InstrFormats.td Refactoring
There is some redundancy at the instruction format level in the x86 .td files. For example, in X86InstrFormats.td: // SSE1 Instruction Templates: // // SSI - SSE1 instructions with XS prefix. class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; // SSE3 Instruction Templates: // S3SI - SSE3 instructions with XSrefix. class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag&g...
2018 May 25
2
[RFC] Formalizing FileCheck Features
...up. The group >> is not executed immediately; instead the next non-NOT directive is >> executed first, and the start of that directive's match range becomes >> the end of the NOT Group's search range. > > Based on the following, that wording is not quite right when a DAG > group follows, so there should probably be some note about that here. So, "the next non-NOT directive or DAG group is executed ... the start of that directive or group's match range ..." ?   >>  (If the next directive is >> LABEL, it has already executed and has a ma...
2005 Oct 23
5
dags repo after 4.2 update
Is anyone else having probs with dags repo after 4.2 update? # yum update Setting up Update Process Setting up repositories http://apt.sw.be/redhat/el4/en/i386/dag/repodata/repomd.xml: [Errno 4] IOError: <urlopen error (101, 'Network is unreachable')> Trying other mirror. Cannot open/read repomd.xml file for repository...
2007 Sep 20
2
[LLVMdev] Building on x86-64
I made my first attempt to build on an x86_64-unknown-linux-gnu system. Is this supposed to work? I get libtools errors (below). The problem seems to be that it finds a 32-bit libltdl rather than the 64-bit libltdl. /home/dag> ls /usr/lib/libltdl.so.3.1.0 /usr/lib/libltdl.so.3.1.0 /home/dag> ls /usr/lib64/libltdl.so.3.1.0 /usr/lib64/libltdl.so.3.1.0 Is this a known problem? I'm not very familiar with how libtools works so I'm a bit hesitant to hack up ltmain.sh....
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
..., ArrayRef<int> Mask, MVT VT, SDValue V1, SDValue V2, const SmallBitVector &Zeroable, const X86Subtarget &Subtarget, SelectionDAG &DAG) { // If we have a single input to the zero element, insert that into V1 if we // can do so cheaply. int NumElts = Mask.size(); int NumV2Elements = count_if(Mask, [NumElts](int M) { return M >= NumElts; }); if (NumV2Elements == 1 && Mask[0] >= NumElts) if (SD...
2009 Dec 01
0
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a
2016 Mar 08
2
FileCheck: combining -DAG and -NOT
Nope. Sorry, your expectation is incorrect. "BETWEEN BEFORE AFTER" would be accepted, because: (1) the first –DAG matches BEFORE; (2) the –NOT range starts at the preceding match-point, i.e. the (end of the) BEFORE, thus does not find BETWEEN; (3) the second –DAG starts at the same point as the –NOT. That is, the first –DAG and the following –NOT *are* ordered; the –NOT and the subsequent –DAG are *not* ordere...
2016 Mar 08
2
FileCheck: combining -DAG and -NOT
If you look at the FileCheck documentation page: http://llvm.org/docs/CommandGuide/FileCheck.html you'll find this intriguing example of combining -DAG with -NOT (slightly amended to avoid some potential confusion): ; CHECK-DAG: BEFORE ; CHECK-NOT: BETWEEN ; CHECK-DAG: AFTER The page says this will reject the sequence "AFTER BEFORE", which is correct. It's intuitively obvious that it will also reject the text "BEFORE BETWEEN...
2005 Nov 02
7
Dag repo
Hi All, Went to Dags page and did not see an entry or Centos for yum configuration. Is Dag ok to use for Centos? If so, how would I enter the info in my dag repo file? Phil
2018 Jun 14
3
[RFC] Formalizing FileCheck Features
A few replies, then I'll post a revised spec v2 which ought to incorporate all the other feedback. If I missed something, give a shout. Actually, I wish there were a way to do that [constrain DAG to a single line] for the sake of matching unordered text on a single line. SAME after DAGs is as close as I can get to that. Maybe we need a CHECK-DAG-SAME. Hmmm. You know, there were cases where people wrote tests that tried to use combo suffixes like that, but of course those directives were...
2020 Oct 13
5
Manipulating DAGs in TableGen
On Tue, Oct 13, 2020 at 10:47 AM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > What do you guys think about the below enhancements? > > 5. !getdagrestype(dag [, index]) - Returns type of result value. If the DAG computes multiple values then return type of 'index'th result. > > 6. !setdagrestype(dag target_dag, type T [, index]) - Set return type of target_dag to T. Use of 'index' is as in 5.(Coupled with the existing (o...
2009 Mar 30
0
[LLVMdev] RFC: X86InstrFormats.td Refactoring
...12, David Greene wrote: > There is some redundancy at the instruction format level in the x86 .td > files. For example, in X86InstrFormats.td: > > // SSE1 Instruction Templates: > // > // SSI - SSE1 instructions with XS prefix. > > class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> > pattern> > > : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; > > // SSE3 Instruction Templates: > // S3SI - SSE3 instructions with XSrefix. > > class S3SI<bits<8> o, Format F, dag out...
2020 Oct 11
2
Manipulating DAGs in TableGen
This is a proposal to enhance TableGen's ability to analyze and manipulate DAGs. Hopefully this will allows more complex DAGs to be built in TableGen. 1. Add a new value suffix. value(index) The value must be a DAG. The index specifies the operator or an operand, whose value is produced. The index can be 0 produce the operator 1...n produc...