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Vincent Lejeune

2012-Oct-25 15:54 UTC

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

> 
> PHIElim and TwoAddress passes leave SSA form.
> May be a missed something in your code but %vreg48 seems to be there 
> after PHI elimination. PHIElim tags those kind of registers as being 
> PHIJoin regs, updating LiveVariables pass, so the regcoalescer is aware 
> of them (some SSA info is still alive but the reg coalescer will 
> invalidate that information after joining intervals). PHIJoin regs 
> doesn't get modified by any other instruction than copies.
> Anyway, IMHO if your code is faulty there should be a bug somewhere else.
> 

It seems the PhiElim is working correctly, the output of --debug-only=regalloc
shows that %vreg48 is a phi-join register, and intervals looks correct to me :

********** COMPUTING LIVE INTERVALS **********
********** Function: main
BB#0:# derived from 
16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
register: %vreg17 +[16r,352r:0)
32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
R600_Reg128:%vreg21 R600_Reg32:%vreg18
register: %vreg21 +[128r,176r:0)
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
register: %vreg23 +[144r,224r:0)
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
R600_TReg32:%vreg15
register: %vreg23 replace range with [144r,160r:1) RESULT:
[144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
register: %vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT:
[176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
R600_TReg32:%vreg16
register: %vreg26 replace range with [224r,240r:1) RESULT:
[224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
register: %vreg27 +[256r,304r:0)
272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27
R600_Reg32:%vreg25
register: %vreg27 replace range with [256r,272r:1) RESULT:
[256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
register: %vreg28 +[288r,320r:0)
304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
register: %vreg3 +[304r,416r:0)
320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3
R600_Reg32:%vreg28
register: %vreg3 replace range with [304r,320r:1) RESULT:
[304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT:
[336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
register: %vreg49 +[432r,448B:0) phi-join +[448B,496r:1)
BB#1:# derived from 
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
register: %vreg5 +[464r,592B:0) +[880B,992r:0)
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0,
0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
register: %vreg29 +[512r,528r:0)
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
register: %vreg30 +[528r,544r:0)
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16;
R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
BB#2:# derived from 
608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg6
register: %vreg39 +[608r,624r:0)
624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39
640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg6
register: %vreg40 +[640r,656r:0)
656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40
672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg6
register: %vreg41 +[672r,688r:0)
688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41
704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42
R600_Reg128:%vreg6
register: %vreg42 +[704r,720r:0)
720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43
R600_Reg128:%vreg1
register: %vreg43 +[736r,752r:0)
752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44
R600_Reg128:%vreg1
register: %vreg44 +[768r,784r:0)
784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45
R600_Reg128:%vreg1
register: %vreg45 +[800r,816r:0)
816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46
R600_Reg128:%vreg1
register: %vreg46 +[832r,848r:0)
848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>,
%T1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>,
%T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
BB#3:# derived from 
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31
R600_Reg128:%vreg6
register: %vreg31 +[896r,912r:0)
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>;
R600_Reg128:%vreg32 R600_Reg32:%vreg31
register: %vreg32 +[912r,944r:0)
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg6
register: %vreg34 +[928r,960r:0)
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
register: %vreg35 +[944r,976r:0)
960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35
R600_Reg32:%vreg34
register: %vreg35 replace range with [944r,960r:1) RESULT:
[944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
register: %vreg36 +[976r,1024r:0)
992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36
R600_Reg32:%vreg5
register: %vreg36 replace range with [976r,992r:1) RESULT:
[976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg6
register: %vreg37 +[1008r,1040r:0)
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
register: %vreg10 +[1024r,1120r:0)
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10
R600_Reg32:%vreg37
register: %vreg10 replace range with [1024r,1040r:1) RESULT:
[1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9
R600_Reg128:%vreg6
register: %vreg9 +[1056r,1104r:0)
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
register: %vreg38 +[1072r,1088r:0)
1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg11,%vreg7,%vreg38
register: %vreg11 +[1088r,1136r:0)
1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9
register: %vreg47 phi-join +[1104r,1168B:2)
1120B%vreg48<def> = COPY %vreg10<kill>; R600_Reg128:%vreg48,%vreg10
register: %vreg48 phi-join +[1120r,1168B:2)
1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
register: %vreg49 phi-join +[1136r,1168B:2)
1152BJUMP <BB#1>, pred:%noreg
Computing live-in reg-units in ABI blocks.
0BBB#0 T1_X#0 T1_Y#0 T1_Z#0 T1_W#0
Created 4 new intervals.
********** INTERVALS **********
T1_W = [0B,16r:0)[848r,864r:1)  0 at 0B-phi 1 at 848r
T1_X = [0B,64r:0)[752r,864r:1)  0 at 0B-phi 1 at 752r
T1_Y = [0B,48r:0)[784r,864r:1)  0 at 0B-phi 1 at 784r
T1_Z = [0B,32r:0)[816r,864r:1)  0 at 0B-phi 1 at 816r
%vreg0 = [384r,592B:0)[880B,1168B:0)  0 at 384r
%vreg1 = [336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
%vreg2 = [112r,400r:0)  0 at 112r
%vreg3 = [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
%vreg5 = [464r,592B:0)[880B,992r:0)  0 at 464r
%vreg6 = [480r,704r:0)[880B,1056r:0)  0 at 480r
%vreg7 = [496r,592B:0)[880B,1088r:0)  0 at 496r
%vreg9 = [1056r,1104r:0)  0 at 1056r
%vreg10 = [1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
%vreg11 = [1088r,1136r:0)  0 at 1088r
%vreg13 = [368r,432r:0)  0 at 368r
%vreg14 = [64r,96r:0)  0 at 64r
%vreg15 = [48r,160r:0)  0 at 48r
%vreg16 = [32r,240r:0)  0 at 32r
%vreg17 = [16r,352r:0)  0 at 16r
%vreg18 = [80r,128r:0)  0 at 80r
%vreg19 = [96r,144r:0)  0 at 96r
%vreg21 = [128r,176r:0)  0 at 128r
%vreg23 = [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
%vreg24 = [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
%vreg25 = [208r,272r:0)  0 at 208r
%vreg26 = [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
%vreg27 = [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
%vreg28 = [288r,320r:0)  0 at 288r
%vreg29 = [512r,528r:0)  0 at 512r
%vreg30 = [528r,544r:0)  0 at 528r
%vreg31 = [896r,912r:0)  0 at 896r
%vreg32 = [912r,944r:0)  0 at 912r
%vreg34 = [928r,960r:0)  0 at 928r
%vreg35 = [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
%vreg36 = [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
%vreg37 = [1008r,1040r:0)  0 at 1008r
%vreg38 = [1072r,1088r:0)  0 at 1072r
%vreg39 = [608r,624r:0)  0 at 608r
%vreg40 = [640r,656r:0)  0 at 640r
%vreg41 = [672r,688r:0)  0 at 672r
%vreg42 = [704r,720r:0)  0 at 704r
%vreg43 = [736r,752r:0)  0 at 736r
%vreg44 = [768r,784r:0)  0 at 768r
%vreg45 = [800r,816r:0)  0 at 800r
%vreg46 = [832r,848r:0)  0 at 832r
%vreg47 = [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at 448B-phi 2
at 1104r
%vreg48 = [416r,448B:0)[448B,480r:1)[1120r,1168B:2)  0 at 416r 1 at 448B-phi 2
at 1120r
%vreg49 = [432r,448B:0)[448B,496r:1)[1136r,1168B:2)  0 at 432r 1 at 448B-phi 2
at 1136r
********** MACHINEINSTRS **********
# Machine code for function main: Post SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W
in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X

0BBB#0: derived from LLVM BB %0
    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
R600_Reg128:%vreg19 R600_TReg32:%vreg14
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
R600_Reg128:%vreg21 R600_Reg32:%vreg18
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
R600_TReg32:%vreg15
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
R600_Reg32:%vreg2
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
R600_TReg32:%vreg16
256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27
R600_Reg32:%vreg25
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3
R600_Reg32:%vreg28
336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
R600_TReg32:%vreg17
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
    Successors according to CFG: BB#1

448BBB#1: derived from LLVM BB %25
    Predecessors according to CFG: BB#0 BB#3
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0,
0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16;
R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
    Successors according to CFG: BB#2(4) BB#3(124)

592BBB#2: derived from LLVM BB %31
    Predecessors according to CFG: BB#1
608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg6
624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39
640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg6
656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40
672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg6
688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41
704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42
R600_Reg128:%vreg6
720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43
R600_Reg128:%vreg1
752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44
R600_Reg128:%vreg1
784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45
R600_Reg128:%vreg1
816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46
R600_Reg128:%vreg1
848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>,
%T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>,
%T2_Y<imp-use,kill>, %T2_X<imp-use,kill>

880BBB#3: derived from LLVM BB %41
    Predecessors according to CFG: BB#1
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31
R600_Reg128:%vreg6
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>;
R600_Reg128:%vreg32 R600_Reg32:%vreg31
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg6
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35
R600_Reg32:%vreg34
976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36
R600_Reg32:%vreg5
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg6
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10
R600_Reg32:%vreg37
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9
R600_Reg128:%vreg6
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg11,%vreg7,%vreg38
1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9
1120B%vreg48<def> = COPY %vreg10<kill>; R600_Reg128:%vreg48,%vreg10
1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
1152BJUMP <BB#1>, pred:%noreg
    Successors according to CFG: BB#1

# End machine code for function main.

********** SIMPLE REGISTER COALESCING **********
********** Function: main
********** JOINING INTERVALS ***********
:
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
Considering merging to R600_Reg32 with %vreg47 in %vreg5
RHS = %vreg5 [464r,592B:0)[880B,992r:0)  0 at 464r
LHS = %vreg47 [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at 448B-phi
2 at 1104r
merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
erased:464r%vreg5<def> = COPY %vreg47<kill>;
R600_Reg32:%vreg5,%vreg47
AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W
%T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X
%T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y
%T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y
%T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X
%T14_Y %T14_Z %T14_W %T15_X %T15_Y %T15_Z %T15_W %T16_X %T16_Y %T16_Z %T16_W
%T17_X %T17_Y %T17_Z %T17_W %T18_X %T18_Y %T18_Z %T18_W %T19_X %T19_Y %T19_Z
%T19_W %T20_X %T20_Y %T20_Z %T20_W %T21_X %T21_Y %T21_Z %T21_W %T22_X %T22_Y
%T22_Z %T22_W %T23_X %T23_Y %T23_Z %T23_W %T24_X %T24_Y %T24_Z %T24_W %T25_X
%T25_Y %T25_Z %T25_W %T26_X %T26_Y %T26_Z %T26_W %T27_X %T27_Y %T27_Z %T27_W
%T28_X %T28_Y %T28_Z %T28_W %T29_X %T29_Y %T29_Z %T29_W %T30_X %T30_Y %T30_Z
%T30_W %T31_X %T31_Y %T31_Z %T31_W %T32_X %T32_Y %T32_Z %T32_W %T33_X %T33_Y
%T33_Z %T33_W %T34_X %T34_Y %T34_Z
 %T34_W %T35_X %T35_Y %T35_Z %T35_W %T36_X %T36_Y %T36_Z %T36_W %T37_X %T37_Y
%T37_Z %T37_W %T38_X %T38_Y %T38_Z %T38_W %T39_X %T39_Y %T39_Z %T39_W %T40_X
%T40_Y %T40_Z %T40_W %T41_X %T41_Y %T41_Z %T41_W %T42_X %T42_Y %T42_Z %T42_W
%T43_X %T43_Y %T43_Z %T43_W %T44_X %T44_Y %T44_Z %T44_W %T45_X %T45_Y %T45_Z
%T45_W %T46_X %T46_Y %T46_Z %T46_W %T47_X %T47_Y %T47_Z %T47_W %T48_X %T48_Y
%T48_Z %T48_W %T49_X %T49_Y %T49_Z %T49_W %T50_X %T50_Y %T50_Z %T50_W %T51_X
%T51_Y %T51_Z %T51_W %T52_X %T52_Y %T52_Z %T52_W %T53_X %T53_Y %T53_Z %T53_W
%T54_X %T54_Y %T54_Z %T54_W %T55_X %T55_Y %T55_Z %T55_W %T56_X %T56_Y %T56_Z
%T56_W %T57_X %T57_Y %T57_Z %T57_W %T58_X %T58_Y %T58_Z %T58_W %T59_X %T59_Y
%T59_Z %T59_W %T60_X %T60_Y %T60_Z %T60_W %T61_X %T61_Y %T61_Z %T61_W %T62_X
%T62_Y %T62_Z %T62_W %T63_X %T63_Y %T63_Z %T63_W %T64_X %T64_Y %T64_Z %T64_W
%T65_X %T65_Y %T65_Z %T65_W %T66_X %T66_Y %T66_Z %T66_W %T67_X %T67_Y %T67_Z
%T67_W %T68_X %T68_Y %T68_Z %T68_W %T69_X
 %T69_Y %T69_Z %T69_W %T70_X %T70_Y %T70_Z %T70_W %T71_X %T71_Y %T71_Z %T71_W
%T72_X %T72_Y %T72_Z %T72_W %T73_X %T73_Y %T73_Z %T73_W %T74_X %T74_Y %T74_Z
%T74_W %T75_X %T75_Y %T75_Z %T75_W %T76_X %T76_Y %T76_Z %T76_W %T77_X %T77_Y
%T77_Z %T77_W %T78_X %T78_Y %T78_Z %T78_W %T79_X %T79_Y %T79_Z %T79_W %T80_X
%T80_Y %T80_Z %T80_W %T81_X %T81_Y %T81_Z %T81_W %T82_X %T82_Y %T82_Z %T82_W
%T83_X %T83_Y %T83_Z %T83_W %T84_X %T84_Y %T84_Z %T84_W %T85_X %T85_Y %T85_Z
%T85_W %T86_X %T86_Y %T86_Z %T86_W %T87_X %T87_Y %T87_Z %T87_W %T88_X %T88_Y
%T88_Z %T88_W %T89_X %T89_Y %T89_Z %T89_W %T90_X %T90_Y %T90_Z %T90_W %T91_X
%T91_Y %T91_Z %T91_W %T92_X %T92_Y %T92_Z %T92_W %T93_X %T93_Y %T93_Z %T93_W
%T94_X %T94_Y %T94_Z %T94_W %T95_X %T95_Y %T95_Z %T95_W %T96_X %T96_Y %T96_Z
%T96_W %T97_X %T97_Y %T97_Z %T97_W %T98_X %T98_Y %T98_Z %T98_W %T99_X %T99_Y
%T99_Z %T99_W %T100_X %T100_Y %T100_Z %T100_W %T101_X %T101_Y %T101_Z %T101_W
%T102_X %T102_Y %T102_Z %T102_W %T103_X
 %T103_Y %T103_Z %T103_W %T104_X %T104_Y %T104_Z %T104_W %T105_X %T105_Y %T105_Z
%T105_W %T106_X %T106_Y %T106_Z %T106_W %T107_X %T107_Y %T107_Z %T107_W %T108_X
%T108_Y %T108_Z %T108_W %T109_X %T109_Y %T109_Z %T109_W %T110_X %T110_Y %T110_Z
%T110_W %T111_X %T111_Y %T111_Z %T111_W %T112_X %T112_Y %T112_Z %T112_W %T113_X
%T113_Y %T113_Z %T113_W %T114_X %T114_Y %T114_Z %T114_W %T115_X %T115_Y %T115_Z
%T115_W %T116_X %T116_Y %T116_Z %T116_W %T117_X %T117_Y %T117_Z %T117_W %T118_X
%T118_Y %T118_Z %T118_W %T119_X %T119_Y %T119_Z %T119_W %T120_X %T120_Y %T120_Z
%T120_W %T121_X %T121_Y %T121_Z %T121_W %T122_X %T122_Y %T122_Z %T122_W %T123_X
%T123_Y %T123_Z %T123_W %T124_X %T124_Y %T124_Z %T124_W %T125_X %T125_Y %T125_Z
%T125_W %T126_X %T126_Y %T126_Z %T126_W %T127_X %T127_Y %T127_Z %T127_W
%ArrayBase448 %ArrayBase449 %ArrayBase450 %ArrayBase451 %ArrayBase452
%ArrayBase453 %ArrayBase454 %ArrayBase455 %ArrayBase456 %ArrayBase457
%ArrayBase458 %ArrayBase459
 %ArrayBase460 %ArrayBase461 %ArrayBase462 %ArrayBase463 %ArrayBase464 ]
updated: 992B%vreg36:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg36
R600_Reg32:%vreg47
Joined. Result = %vreg47[400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)
 0 at 400r 1 at 448B-phi 2 at 1104r
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
Considering merging to R600_Reg128 with %vreg48 in %vreg6
RHS = %vreg6 [480r,704r:0)[880B,1056r:0)  0 at 480r
LHS = %vreg48 [416r,448B:0)[448B,480r:1)[1120r,1168B:2)  0 at 416r 1 at 448B-phi
2 at 1120r
merge %vreg6:0 at 480r into %vreg48:1 at 448B --> @448B
erased:480r%vreg6<def> = COPY %vreg48<kill>;
R600_Reg128:%vreg6,%vreg48
AllocationOrder(R600_Reg128) = [ %T0_XYZW %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW
%T5_XYZW %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW
%T13_XYZW %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW
%T21_XYZW %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW
%T29_XYZW %T30_XYZW %T31_XYZW %T32_XYZW %T33_XYZW %T34_XYZW %T35_XYZW %T36_XYZW
%T37_XYZW %T38_XYZW %T39_XYZW %T40_XYZW %T41_XYZW %T42_XYZW %T43_XYZW %T44_XYZW
%T45_XYZW %T46_XYZW %T47_XYZW %T48_XYZW %T49_XYZW %T50_XYZW %T51_XYZW %T52_XYZW
%T53_XYZW %T54_XYZW %T55_XYZW %T56_XYZW %T57_XYZW %T58_XYZW %T59_XYZW %T60_XYZW
%T61_XYZW %T62_XYZW %T63_XYZW %T64_XYZW %T65_XYZW %T66_XYZW %T67_XYZW %T68_XYZW
%T69_XYZW %T70_XYZW %T71_XYZW %T72_XYZW %T73_XYZW %T74_XYZW %T75_XYZW %T76_XYZW
%T77_XYZW %T78_XYZW %T79_XYZW %T80_XYZW %T81_XYZW %T82_XYZW %T83_XYZW %T84_XYZW
%T85_XYZW %T86_XYZW %T87_XYZW %T88_XYZW %T89_XYZW %T90_XYZW %T91_XYZW %T92_XYZW
%T93_XYZW
 %T94_XYZW %T95_XYZW %T96_XYZW %T97_XYZW %T98_XYZW %T99_XYZW %T100_XYZW
%T101_XYZW %T102_XYZW %T103_XYZW %T104_XYZW %T105_XYZW %T106_XYZW %T107_XYZW
%T108_XYZW %T109_XYZW %T110_XYZW %T111_XYZW %T112_XYZW %T113_XYZW %T114_XYZW
%T115_XYZW %T116_XYZW %T117_XYZW %T118_XYZW %T119_XYZW %T120_XYZW %T121_XYZW
%T122_XYZW %T123_XYZW %T124_XYZW %T125_XYZW %T126_XYZW %T127_XYZW ]
updated: 896B%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31
R600_Reg128:%vreg48
updated: 928B%vreg34<def> = COPY %vreg48:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg48
updated: 1008B%vreg37<def> = COPY %vreg48:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg48
updated: 1056B%vreg9<def> = COPY %vreg48:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg48
updated: 608B%vreg39<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg48
updated: 640B%vreg40<def> = COPY %vreg48:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg48
updated: 672B%vreg41<def> = COPY %vreg48:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg48
updated: 704B%vreg42<def> = COPY %vreg48:sel_w; R600_Reg32:%vreg42
R600_Reg128:%vreg48
Joined. Result = %vreg48[416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)
 0 at 416r 1 at 448B-phi 2 at 1120r
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
Considering merging to R600_Reg32 with %vreg49 in %vreg7
RHS = %vreg7 [496r,592B:0)[880B,1088r:0)  0 at 496r
LHS = %vreg49 [432r,448B:0)[448B,496r:1)[1136r,1168B:2)  0 at 432r 1 at 448B-phi
2 at 1136r
merge %vreg7:0 at 496r into %vreg49:1 at 448B --> @448B
erased:496r%vreg7<def> = COPY %vreg49<kill>;
R600_Reg32:%vreg7,%vreg49
updated: 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0,
%vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg49
updated: 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg11,%vreg49,%vreg38
Joined. Result = %vreg49[432r,448B:0)[448B,592B:1)[880B,1088r:1)[1136r,1168B:2)
 0 at 432r 1 at 448B-phi 2 at 1136r
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
Considering merging to R600_Reg32 with %vreg29 in %vreg30
RHS = %vreg29 [512r,528r:0)  0 at 512r
LHS = %vreg30 [528r,544r:0)  0 at 528r
merge %vreg30:0 at 528r into %vreg29:0 at 512r --> @512r
erased:528r%vreg30<def> = COPY %vreg29<kill>;
R600_Reg32:%vreg30,%vreg29
updated: 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0,
%vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg0,%vreg49
Joined. Result = %vreg30[512r,544r:0)  0 at 512r
:
896B%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31
R600_Reg128:%vreg48
Considering merging to R600_Reg128 with %vreg31 in %vreg48:sel_x
RHS = %vreg31 [896r,912r:0)  0 at 896r
LHS = %vreg48 [416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)  0 at 416r
1 at 448B-phi 2 at 1120r
merge %vreg31:0 at 896r into %vreg48:1 at 448B --> @448B
erased:896r%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31
R600_Reg128:%vreg48
updated: 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;
R600_Reg128:%vreg32,%vreg48
Joined. Result = %vreg48[416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)
 0 at 416r 1 at 448B-phi 2 at 1120r
912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;
R600_Reg128:%vreg32,%vreg48
Considering merging to R600_Reg128 with %vreg48 in %vreg32
RHS = %vreg48 [416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)  0 at 416r
1 at 448B-phi 2 at 1120r
LHS = %vreg32 [912r,944r:0)  0 at 912r
merge %vreg32:0 at 912r into %vreg48:1 at 448B --> @448B
erased:912r%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;
R600_Reg128:%vreg32,%vreg48
updated: 416B%vreg32<def> = COPY %vreg3<kill>;
R600_Reg128:%vreg32,%vreg3
updated: 1120B%vreg32<def> = COPY %vreg10<kill>;
R600_Reg128:%vreg32,%vreg10
updated: 928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg32
updated: 1008B%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg32
updated: 1056B%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg32
updated: 608B%vreg39<def> = COPY %vreg32:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg32
updated: 640B%vreg40<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg32
updated: 672B%vreg41<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg32
updated: 704B%vreg42<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg42
R600_Reg128:%vreg32
Joined. Result = %vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
 0 at 448B-phi 1 at 416r 2 at 1120r
928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg32
Considering merging to R600_Reg128 with %vreg34 in %vreg32:sel_y
RHS = %vreg34 [928r,960r:0)  0 at 928r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg34:0 at 928r into %vreg32:0 at 448B --> @448B
erased:928r%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg32
updated: 960B%vreg35:sel_y<def> = COPY %vreg32:sel_y;
R600_Reg128:%vreg35,%vreg32
Joined. Result = %vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
 0 at 448B-phi 1 at 416r 2 at 1120r
944B%vreg35<def> = COPY %vreg32; R600_Reg128:%vreg35,%vreg32
Considering merging to R600_Reg128 with %vreg32 in %vreg35
RHS = %vreg35 [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg35:1 at 944r into %vreg32:0 at 448B --> @448B
merge %vreg35:0 at 960r into %vreg32:0 at 448B --> @448B
erased:960r%vreg35:sel_y<def> = COPY %vreg32:sel_y;
R600_Reg128:%vreg35,%vreg32
erased:944r%vreg35<def> = COPY %vreg32; R600_Reg128:%vreg35,%vreg32
updated: 976B%vreg36<def> = COPY %vreg32; R600_Reg128:%vreg36,%vreg32
Joined. Result = %vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
 0 at 448B-phi 1 at 416r 2 at 1120r
976B%vreg36<def> = COPY %vreg32; R600_Reg128:%vreg36,%vreg32
Considering merging to R600_Reg128 with %vreg32 in %vreg36
RHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg36:1 at 976r into %vreg32:0 at 448B --> @448B
conflict at %vreg36:0 at 992r
taints local %vreg32:0 at 880B to 1056r
tainted lanes used by: %vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg32
Interference!
992B%vreg36:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg36
R600_Reg32:%vreg47
Considering merging to R600_Reg128 with %vreg47 in %vreg36:sel_z
RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at 400r
1 at 448B-phi 2 at 1104r
LHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
merge %vreg36:0 at 992r into %vreg47:1 at 448B --> @448B
interference at %vreg36:1 at 976r
Interference!
1008B%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg32
Considering merging to R600_Reg128 with %vreg37 in %vreg32:sel_w
RHS = %vreg37 [1008r,1040r:0)  0 at 1008r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg37:0 at 1008r into %vreg32:0 at 448B --> @448B
erased:1008r%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37
R600_Reg128:%vreg32
updated: 1040B%vreg10:sel_w<def> = COPY %vreg32:sel_w;
R600_Reg128:%vreg10,%vreg32
Joined. Result = %vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
 0 at 448B-phi 1 at 416r 2 at 1120r
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
Considering merging to R600_Reg128 with %vreg36 in %vreg10
RHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
LHS = %vreg10 [1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
merge %vreg10:1 at 1024r into %vreg36:0 at 992r --> @992r
erased:1024r%vreg10<def> = COPY %vreg36<kill>;
R600_Reg128:%vreg10,%vreg36
updated: 976B%vreg10<def> = COPY %vreg32; R600_Reg128:%vreg10,%vreg32
updated: 992B%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10
R600_Reg32:%vreg47
Joined. Result = %vreg10[976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1
at 992r 2 at 1040r
1040B%vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32
Considering merging to R600_Reg128 with %vreg32 in %vreg10
RHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
LHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at 992r 2
at 1040r
merge %vreg10:0 at 976r into %vreg32:0 at 448B --> @448B
merge %vreg10:2 at 1040r into %vreg32:0 at 448B --> @448B
merge %vreg32:2 at 1120r into %vreg10:2 at 1040r --> @448B
conflict at %vreg10:1 at 992r
taints local %vreg32:0 at 880B to 1056r
tainted lanes used by: %vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg32
Interference!
1056B%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg32
Considering merging to R600_Reg128 with %vreg9 in %vreg32:sel_z
RHS = %vreg9 [1056r,1104r:0)  0 at 1056r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg9:0 at 1056r into %vreg32:0 at 448B --> @448B
erased:1056r%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9
R600_Reg128:%vreg32
updated: 1104B%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47
R600_Reg128:%vreg32
Joined. Result = %vreg32[416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2)
 0 at 448B-phi 1 at 416r 2 at 1120r
1104B%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47
R600_Reg128:%vreg32
Considering merging to R600_Reg128 with %vreg47 in %vreg32:sel_z
RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at 400r
1 at 448B-phi 2 at 1104r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
interference at %vreg32:1 at 416r
Interference!
1120B%vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10
Considering merging to R600_Reg128 with %vreg10 in %vreg32
RHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at 992r 2
at 1040r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2)  0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg10:0 at 976r into %vreg32:0 at 448B --> @448B
merge %vreg10:2 at 1040r into %vreg32:0 at 448B --> @448B
merge %vreg32:2 at 1120r into %vreg10:2 at 1040r --> @448B
conflict at %vreg10:1 at 992r
taints local %vreg32:0 at 880B to 1104r
tainted lanes used by: %vreg47<def> = COPY %vreg32:sel_z;
R600_Reg32:%vreg47 R600_Reg128:%vreg32
Extending: %vreg32   result = [416r,448B:1)[448B,704r:0)[880B,1168B:0)  0 at
448B-phi 1 at 416r
Shrink: [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at 992r 2 at
1040r
Shrunk: [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at 992r 2 at
1040r
Trivial!
1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
Considering merging to R600_Reg32 with %vreg11 in %vreg49
RHS = %vreg11 [1088r,1136r:0)  0 at 1088r
LHS = %vreg49 [432r,448B:0)[448B,592B:1)[880B,1088r:1)[1136r,1168B:2)  0 at 432r
1 at 448B-phi 2 at 1136r
merge %vreg49:2 at 1136r into %vreg11:0 at 1088r --> @1088r
erased:1136r%vreg49<def> = COPY %vreg11<kill>;
R600_Reg32:%vreg49,%vreg11
updated: 1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg49,%vreg38
Joined. Result = %vreg49[432r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)
 0 at 432r 1 at 448B-phi 2 at 1088r
:
16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
Considering merging %vreg17 with %T1_W
Can only merge into reserved registers.
32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
Considering merging %vreg16 with %T1_Z
Can only merge into reserved registers.
48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
Considering merging %vreg15 with %T1_Y
Can only merge into reserved registers.
64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
Considering merging %vreg14 with %T1_X
Can only merge into reserved registers.
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
Considering merging %vreg18 with %C1_X
RHS = %vreg18 [80r,128r:0)  0 at 80r
updated: 128B%vreg21:sel_x<def,read-undef> = COPY %C1_X;
R600_Reg128:%vreg21
Joined. Result = %C1_X
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
R600_Reg128:%vreg19 R600_TReg32:%vreg14
Considering merging to R600_Reg128 with %vreg14 in %vreg19:sel_x
RHS = %vreg14 [64r,96r:0)  0 at 64r
LHS = %vreg19 [96r,144r:0)  0 at 96r
merge %vreg19:0 at 96r into %vreg14:0 at 64r --> @64r
erased:96r%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
R600_Reg128:%vreg19 R600_TReg32:%vreg14
updated: 64B%vreg19:sel_x<def,read-undef> = COPY %T1_X;
R600_Reg128:%vreg19
Joined. Result = %vreg19[64r,144r:0)  0 at 64r
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
Considering merging %vreg2 with %C1_Y
RHS = %vreg2 [112r,400r:0)  0 at 112r
updated: 400B%vreg47<def> = COPY %C1_Y; R600_Reg32:%vreg47
updated: 192B%vreg24:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg24
Joined. Result = %C1_Y
128B%vreg21:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg21
Not coalescable.
144B%vreg23<def> = COPY %vreg19; R600_Reg128:%vreg23,%vreg19
Considering merging to R600_Reg128 with %vreg19 in %vreg23
RHS = %vreg19 [64r,144r:0)  0 at 64r
LHS = %vreg23 [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
merge %vreg23:1 at 144r into %vreg19:0 at 64r --> @64r
erased:144r%vreg23<def> = COPY %vreg19; R600_Reg128:%vreg23,%vreg19
updated: 64B%vreg23:sel_x<def,read-undef> = COPY %T1_X;
R600_Reg128:%vreg23
Joined. Result = %vreg23[64r,160r:0)[160r,224r:1)  0 at 64r 1 at 160r
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
R600_TReg32:%vreg15
Considering merging to R600_Reg128 with %vreg15 in %vreg23:sel_y
RHS = %vreg15 [48r,160r:0)  0 at 48r
LHS = %vreg23 [64r,160r:0)[160r,224r:1)  0 at 64r 1 at 160r
merge %vreg23:1 at 160r into %vreg15:0 at 48r --> @48r
pruned %vreg15 at 64r: [48r,64r:0)  0 at 48r
pruned all of %vreg23 at 160r: [64r,160r:0)  0 at 64r 1 at 160r
erased:160r%vreg23:sel_y<def> = COPY %vreg15<kill>;
R600_Reg128:%vreg23 R600_TReg32:%vreg15
restoring liveness to 3 points: [48r,64r:0)[64r,160r:1)  0 at 48r 1 at 64r
updated: 48B%vreg23:sel_y<def,read-undef> = COPY %T1_Y;
R600_Reg128:%vreg23
Joined. Result = %vreg23[48r,64r:0)[64r,224r:1)  0 at 48r 1 at 64r
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
Considering merging to R600_Reg128 with %vreg21 in %vreg24
RHS = %vreg21 [128r,176r:0)  0 at 128r
LHS = %vreg24 [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
merge %vreg24:1 at 176r into %vreg21:0 at 128r --> @128r
erased:176r%vreg24<def> = COPY %vreg21<kill>;
R600_Reg128:%vreg24,%vreg21
updated: 128B%vreg24:sel_x<def,read-undef> = COPY %C1_X;
R600_Reg128:%vreg24
Joined. Result = %vreg24[128r,192r:0)[192r,256r:1)  0 at 128r 1 at 192r
192B%vreg24:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg24
Not coalescable.
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
Considering merging %vreg25 with %C1_Z
RHS = %vreg25 [208r,272r:0)  0 at 208r
updated: 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
Joined. Result = %C1_Z
224B%vreg26<def> = COPY %vreg23; R600_Reg128:%vreg26,%vreg23
Considering merging to R600_Reg128 with %vreg23 in %vreg26
RHS = %vreg23 [48r,64r:0)[64r,224r:1)  0 at 48r 1 at 64r
LHS = %vreg26 [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
merge %vreg26:1 at 224r into %vreg23:1 at 64r --> @64r
erased:224r%vreg26<def> = COPY %vreg23; R600_Reg128:%vreg26,%vreg23
updated: 48B%vreg26:sel_y<def,read-undef> = COPY %T1_Y;
R600_Reg128:%vreg26
updated: 64B%vreg26:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg26
Joined. Result = %vreg26[48r,64r:0)[64r,240r:1)[240r,336r:2)  0 at 48r 1 at 64r
2 at 240r
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
R600_TReg32:%vreg16
Considering merging to R600_Reg128 with %vreg16 in %vreg26:sel_z
RHS = %vreg16 [32r,240r:0)  0 at 32r
LHS = %vreg26 [48r,64r:0)[64r,240r:1)[240r,336r:2)  0 at 48r 1 at 64r 2 at 240r
merge %vreg26:2 at 240r into %vreg16:0 at 32r --> @32r
pruned %vreg16 at 48r: [32r,48r:0)  0 at 32r
pruned %vreg16 at 64r: [32r,48r:0)  0 at 32r
pruned all of %vreg26 at 240r: [48r,64r:0)[64r,240r:1)  0 at 48r 1 at 64r 2 at
240r
erased:240r%vreg26:sel_z<def> = COPY %vreg16<kill>;
R600_Reg128:%vreg26 R600_TReg32:%vreg16
restoring liveness to 4 points: [32r,48r:0)[48r,64r:1)[64r,240r:2)  0 at 32r 1
at 48r 2 at 64r
updated: 32B%vreg26:sel_z<def,read-undef> = COPY %T1_Z;
R600_Reg128:%vreg26
Joined. Result = %vreg26[32r,48r:0)[48r,64r:1)[64r,336r:2)  0 at 32r 1 at 48r 2
at 64r
256B%vreg27<def> = COPY %vreg24; R600_Reg128:%vreg27,%vreg24
Considering merging to R600_Reg128 with %vreg24 in %vreg27
RHS = %vreg24 [128r,192r:0)[192r,256r:1)  0 at 128r 1 at 192r
LHS = %vreg27 [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
merge %vreg27:1 at 256r into %vreg24:1 at 192r --> @192r
erased:256r%vreg27<def> = COPY %vreg24; R600_Reg128:%vreg27,%vreg24
updated: 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X;
R600_Reg128:%vreg27
updated: 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
Joined. Result = %vreg27[128r,192r:0)[192r,272r:1)[272r,304r:2)  0 at 128r 1 at
192r 2 at 272r
272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
Not coalescable.
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
Considering merging %vreg28 with %C1_W
RHS = %vreg28 [288r,320r:0)  0 at 288r
updated: 320B%vreg3:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg3
Joined. Result = %C1_W
304B%vreg3<def> = COPY %vreg27; R600_Reg128:%vreg3,%vreg27
Considering merging to R600_Reg128 with %vreg27 in %vreg3
RHS = %vreg3 [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
LHS = %vreg27 [128r,192r:0)[192r,272r:1)[272r,304r:2)  0 at 128r 1 at 192r 2 at
272r
merge %vreg3:1 at 304r into %vreg27:2 at 272r --> @272r
erased:304r%vreg3<def> = COPY %vreg27; R600_Reg128:%vreg3,%vreg27
updated: 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
updated: 416B%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
Joined. Result = %vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,416r:3)  0
at 128r 1 at 192r 2 at 272r 3 at 320r
320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
Not coalescable.
336B%vreg1<def> = COPY %vreg26; R600_Reg128:%vreg1,%vreg26
Considering merging to R600_Reg128 with %vreg26 in %vreg1
RHS = %vreg26 [32r,48r:0)[48r,64r:1)[64r,336r:2)  0 at 32r 1 at 48r 2 at 64r
LHS = %vreg1 [336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
merge %vreg1:1 at 336r into %vreg26:2 at 64r --> @64r
erased:336r%vreg1<def> = COPY %vreg26; R600_Reg128:%vreg1,%vreg26
updated: 32B%vreg1:sel_z<def,read-undef> = COPY %T1_Z; R600_Reg128:%vreg1
updated: 64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
updated: 48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
Joined. Result =
%vreg1[32r,48r:0)[48r,64r:1)[64r,352r:2)[352r,832r:3)[880B,1168B:3)  0 at 32r 1
at 48r 2 at 64r 3 at 352r
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
R600_TReg32:%vreg17
Considering merging to R600_Reg128 with %vreg17 in %vreg1:sel_w
RHS = %vreg17 [16r,352r:0)  0 at 16r
LHS = %vreg1 [32r,48r:0)[48r,64r:1)[64r,352r:2)[352r,832r:3)[880B,1168B:3)  0 at
32r 1 at 48r 2 at 64r 3 at 352r
merge %vreg1:3 at 352r into %vreg17:0 at 16r --> @16r
pruned %vreg17 at 32r: [16r,32r:0)  0 at 16r
pruned %vreg17 at 48r: [16r,32r:0)  0 at 16r
pruned %vreg17 at 64r: [16r,32r:0)  0 at 16r
pruned all of %vreg1 at 352r: [32r,48r:0)[48r,64r:1)[64r,352r:2)  0 at 32r 1 at
48r 2 at 64r 3 at 352r
erased:352r%vreg1:sel_w<def> = COPY %vreg17<kill>;
R600_Reg128:%vreg1 R600_TReg32:%vreg17
restoring liveness to 8 points: [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,352r:3)  0
at 16r 1 at 32r 2 at 48r 3 at 64r
updated: 16B%vreg1:sel_w<def,read-undef> = COPY %T1_W; R600_Reg128:%vreg1
Joined. Result =
%vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r 3 at 64r
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
Considering merging %vreg0 with %C0_X
RHS = %vreg0 [384r,592B:0)[880B,1168B:0)  0 at 384r
updated: 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0,
%vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
Joined. Result = %C0_X
400B%vreg47<def> = COPY %C1_Y; R600_Reg32:%vreg47
Considering merging %vreg47 with %C1_Y
Cannot join defs into reserved register.
416B%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
Considering merging to R600_Reg128 with %vreg27 in %vreg32
RHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1168B:0)  0 at 448B-phi 1 at 416r
LHS = %vreg27 [128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,416r:3)  0 at 128r 1
at 192r 2 at 272r 3 at 320r
merge %vreg32:1 at 416r into %vreg27:3 at 320r --> @320r
erased:416r%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
updated: 608B%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg27
updated: 640B%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg27
updated: 672B%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg27
updated: 704B%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42
R600_Reg128:%vreg27
updated: 976B%vreg10<def> = COPY %vreg27; R600_Reg128:%vreg10,%vreg27
updated: 1040B%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w;
R600_Reg128:%vreg10,%vreg27
updated: 1104B%vreg47<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg47
R600_Reg128:%vreg27
Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Considering merging to R600_Reg32 with %vreg13 in %vreg49
RHS = %vreg13 [368r,432r:0)  0 at 368r
LHS = %vreg49 [432r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at 432r
1 at 448B-phi 2 at 1088r
merge %vreg49:0 at 432r into %vreg13:0 at 368r --> @368r
erased:432r%vreg49<def> = COPY %vreg13<kill>;
R600_Reg32:%vreg49,%vreg13
updated: 368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
Joined. Result = %vreg49[368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)
 0 at 368r 1 at 448B-phi 2 at 1088r
:
608B%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg27
Considering merging to R600_Reg128 with %vreg39 in %vreg27:sel_x
RHS = %vreg39 [608r,624r:0)  0 at 608r
LHS = %vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
merge %vreg39:0 at 608r into %vreg27:4 at 448B --> @448B
erased:608r%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39
R600_Reg128:%vreg27
updated: 624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
Considering merging %vreg27 with %T2_XYZW
Can only merge into reserved registers.
640B%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg27
Considering merging to R600_Reg128 with %vreg40 in %vreg27:sel_y
RHS = %vreg40 [640r,656r:0)  0 at 640r
LHS = %vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
merge %vreg40:0 at 640r into %vreg27:4 at 448B --> @448B
erased:640r%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40
R600_Reg128:%vreg27
updated: 656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
Considering merging %vreg27 with %T2_XYZW
Can only merge into reserved registers.
672B%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg27
Considering merging to R600_Reg128 with %vreg41 in %vreg27:sel_z
RHS = %vreg41 [672r,688r:0)  0 at 672r
LHS = %vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
merge %vreg41:0 at 672r into %vreg27:4 at 448B --> @448B
erased:672r%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41
R600_Reg128:%vreg27
updated: 688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
Considering merging %vreg27 with %T2_XYZW
Can only merge into reserved registers.
704B%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42
R600_Reg128:%vreg27
Considering merging to R600_Reg128 with %vreg42 in %vreg27:sel_w
RHS = %vreg42 [704r,720r:0)  0 at 704r
LHS = %vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
merge %vreg42:0 at 704r into %vreg27:4 at 448B --> @448B
erased:704r%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42
R600_Reg128:%vreg27
updated: 720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
Considering merging %vreg27 with %T2_XYZW
Can only merge into reserved registers.
736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43
R600_Reg128:%vreg1
Considering merging to R600_Reg128 with %vreg43 in %vreg1:sel_x
RHS = %vreg43 [736r,752r:0)  0 at 736r
LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at
16r 1 at 32r 2 at 48r 3 at 64r
merge %vreg43:0 at 736r into %vreg1:3 at 64r --> @64r
erased:736r%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43
R600_Reg128:%vreg1
updated: 752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
Joined. Result =
%vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r 3 at 64r
752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
Considering merging %vreg1 with %T1_XYZW
Can only merge into reserved registers.
768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44
R600_Reg128:%vreg1
Considering merging to R600_Reg128 with %vreg44 in %vreg1:sel_y
RHS = %vreg44 [768r,784r:0)  0 at 768r
LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at
16r 1 at 32r 2 at 48r 3 at 64r
merge %vreg44:0 at 768r into %vreg1:3 at 64r --> @64r
erased:768r%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44
R600_Reg128:%vreg1
updated: 784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
Joined. Result =
%vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r 3 at 64r
784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
Considering merging %vreg1 with %T1_XYZW
Can only merge into reserved registers.
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45
R600_Reg128:%vreg1
Considering merging to R600_Reg128 with %vreg45 in %vreg1:sel_z
RHS = %vreg45 [800r,816r:0)  0 at 800r
LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at
16r 1 at 32r 2 at 48r 3 at 64r
merge %vreg45:0 at 800r into %vreg1:3 at 64r --> @64r
erased:800r%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45
R600_Reg128:%vreg1
updated: 816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
Joined. Result =
%vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r 3 at 64r
816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
Considering merging %vreg1 with %T1_XYZW
Can only merge into reserved registers.
832B%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46
R600_Reg128:%vreg1
Considering merging to R600_Reg128 with %vreg46 in %vreg1:sel_w
RHS = %vreg46 [832r,848r:0)  0 at 832r
LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at
16r 1 at 32r 2 at 48r 3 at 64r
merge %vreg46:0 at 832r into %vreg1:3 at 64r --> @64r
erased:832r%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46
R600_Reg128:%vreg1
updated: 848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
Joined. Result =
%vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r 3 at 64r
848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
Considering merging %vreg1 with %T1_XYZW
Can only merge into reserved registers.
976B%vreg10<def> = COPY %vreg27; R600_Reg128:%vreg10,%vreg27
Considering merging to R600_Reg128 with %vreg27 in %vreg10
RHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at 992r 2
at 1040r
LHS = %vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
merge %vreg10:0 at 976r into %vreg27:4 at 448B --> @448B
interference at %vreg10:1 at 992r
Interference!
992B%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10
R600_Reg32:%vreg47
Considering merging to R600_Reg128 with %vreg47 in %vreg10:sel_z
RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at 400r
1 at 448B-phi 2 at 1104r
LHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at 992r 2
at 1040r
interference at %vreg10:0 at 976r
Interference!
1040B%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w;
R600_Reg128:%vreg10,%vreg27
Copy is dead.
Deleting dead def 1040r%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w;
R600_Reg128:%vreg10,%vreg27
Shrink:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
 live-in at 592B
 live-in at 880B
Shrunk:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
Shrink: [976r,992r:0)[992r,1040r:1)  0 at 976r 1 at 992r
All defs dead: 992r%vreg10:sel_z<def,dead> = COPY %vreg47;
R600_Reg128:%vreg10 R600_Reg32:%vreg47
Shrunk: [976r,992r:0)[992r,992d:1)  0 at 976r 1 at 992r
Deleting dead def 992r%vreg10:sel_z<def,dead> = COPY %vreg47;
R600_Reg128:%vreg10 R600_Reg32:%vreg47
Shrink: [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at 400r 1 at
448B-phi 2 at 1104r
All defs dead: 400r%vreg47<def,dead> = COPY %C1_Y; R600_Reg32:%vreg47
Dead PHI at invalid may separate interval
All defs dead: 1104r%vreg47<def,dead> = COPY %vreg27:sel_z;
R600_Reg32:%vreg47 R600_Reg128:%vreg27
Shrunk: [400r,400d:0)[1104r,1104d:2)  0 at 400r 1 at x 2 at 1104r
2 components: [400r,400d:0)[1104r,1104d:1)  0 at 400r 1 at 1104r
[400r,400d:0)  0 at 400r
[1104r,1104d:0)  0 at 1104r
Deleting dead def 1104r%vreg50<def,dead> = COPY %vreg27:sel_z;
R600_Reg32:%vreg50 R600_Reg128:%vreg27
Deleting dead def 400r%vreg47<def,dead> = COPY %C1_Y; R600_Reg32:%vreg47
Shrink:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
 live-in at 592B
 live-in at 880B
Shrunk:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
Shrink: [976r,992r:0)  0 at 976r
All defs dead: 976r%vreg10<def,dead> = COPY %vreg27;
R600_Reg128:%vreg10,%vreg27
Shrunk: [976r,976d:0)  0 at 976r
Deleting dead def 976r%vreg10<def,dead> = COPY %vreg27;
R600_Reg128:%vreg10,%vreg27
Shrink:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
 live-in at 592B
 live-in at 880B
Shrunk:
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
Trying to inflate 0 regs.
********** INTERVALS **********
C0_X = EMPTY
C1_W = EMPTY
C1_X = EMPTY
C1_Y = EMPTY
C1_Z = EMPTY
T1_W = [0B,16r:0)[848r,864r:1)  0 at 0B-phi 1 at 848r
T1_X = [0B,64r:0)[752r,864r:1)  0 at 0B-phi 1 at 752r
T1_Y = [0B,48r:0)[784r,864r:1)  0 at 0B-phi 1 at 784r
T1_Z = [0B,32r:0)[816r,864r:1)  0 at 0B-phi 1 at 816r
%vreg1 = [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at 16r 1
at 32r 2 at 48r 3 at 64r
%vreg27 =
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
%vreg30 = [512r,544r:0)  0 at 512r
%vreg38 = [1072r,1088r:0)  0 at 1072r
%vreg49 = [368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at 368r 1
at 448B-phi 2 at 1088r
********** MACHINEINSTRS **********
# Machine code for function main: Post SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W
in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X

0BBB#0: derived from LLVM BB %0
    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%vreg1:sel_w<def,read-undef> = COPY %T1_W; R600_Reg128:%vreg1
32B%vreg1:sel_z<def> = COPY %T1_Z; R600_Reg128:%vreg1
48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27
192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
    Successors according to CFG: BB#1

448BBB#1: derived from LLVM BB %25
    Predecessors according to CFG: BB#0 BB#3
512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0,
0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
544B%PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
    Successors according to CFG: BB#2(4) BB#3(124)

592BBB#2: derived from LLVM BB %31
    Predecessors according to CFG: BB#1
624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>,
%T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>,
%T2_Y<imp-use,kill>, %T2_X<imp-use,kill>

880BBB#3: derived from LLVM BB %41
    Predecessors according to CFG: BB#1
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg49,%vreg38
1152BJUMP <BB#1>, pred:%noreg
    Successors according to CFG: BB#1

# End machine code for function main.

********** DEBUG VARIABLES **********
********** GREEDY REGISTER ALLOCATION **********
********** Function: main

selectOrSplit R600_Reg128:%vreg1
[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at 16r 1 at 32r 2
at 48r 3 at 64r
AllocationOrder(R600_Reg128) = [ %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW %T5_XYZW
%T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW %T13_XYZW
%T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW %T21_XYZW
%T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW %T29_XYZW
%T30_XYZW %T31_XYZW %T32_XYZW %T33_XYZW %T34_XYZW %T35_XYZW %T36_XYZW %T37_XYZW
%T38_XYZW %T39_XYZW %T40_XYZW %T41_XYZW %T42_XYZW %T43_XYZW %T44_XYZW %T45_XYZW
%T46_XYZW %T47_XYZW %T48_XYZW %T49_XYZW %T50_XYZW %T51_XYZW %T52_XYZW %T53_XYZW
%T54_XYZW %T55_XYZW %T56_XYZW %T57_XYZW %T58_XYZW %T59_XYZW %T60_XYZW %T61_XYZW
%T62_XYZW %T63_XYZW %T64_XYZW %T65_XYZW %T66_XYZW %T67_XYZW %T68_XYZW %T69_XYZW
%T70_XYZW %T71_XYZW %T72_XYZW %T73_XYZW %T74_XYZW %T75_XYZW %T76_XYZW %T77_XYZW
%T78_XYZW %T79_XYZW %T80_XYZW %T81_XYZW %T82_XYZW %T83_XYZW %T84_XYZW %T85_XYZW
%T86_XYZW %T87_XYZW %T88_XYZW %T89_XYZW %T90_XYZW %T91_XYZW %T92_XYZW %T93_XYZW
%T94_XYZW
 %T95_XYZW %T96_XYZW %T97_XYZW %T98_XYZW %T99_XYZW %T100_XYZW %T101_XYZW
%T102_XYZW %T103_XYZW %T104_XYZW %T105_XYZW %T106_XYZW %T107_XYZW %T108_XYZW
%T109_XYZW %T110_XYZW %T111_XYZW %T112_XYZW %T113_XYZW %T114_XYZW %T115_XYZW
%T116_XYZW %T117_XYZW %T118_XYZW %T119_XYZW %T120_XYZW %T121_XYZW %T122_XYZW
%T123_XYZW %T124_XYZW %T125_XYZW %T126_XYZW %T127_XYZW ]
assigning %vreg1 to %T1_XYZW: T1_W T1_X T1_Y T1_Z

selectOrSplit R600_Reg128:%vreg27
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
 0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
assigning %vreg27 to %T2_XYZW: T2_W T2_X T2_Y T2_Z

selectOrSplit R600_Reg32:%vreg49
[368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at 368r 1 at 448B-phi
2 at 1088r
AllocationOrder(R600_Reg32) = [ %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W
%T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W %T6_X
%T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X %T9_Y
%T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %T11_Z %T11_W %T12_X
%T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X %T14_Y %T14_Z %T14_W
%T15_X %T15_Y %T15_Z %T15_W %T16_X %T16_Y %T16_Z %T16_W %T17_X %T17_Y %T17_Z
%T17_W %T18_X %T18_Y %T18_Z %T18_W %T19_X %T19_Y %T19_Z %T19_W %T20_X %T20_Y
%T20_Z %T20_W %T21_X %T21_Y %T21_Z %T21_W %T22_X %T22_Y %T22_Z %T22_W %T23_X
%T23_Y %T23_Z %T23_W %T24_X %T24_Y %T24_Z %T24_W %T25_X %T25_Y %T25_Z %T25_W
%T26_X %T26_Y %T26_Z %T26_W %T27_X %T27_Y %T27_Z %T27_W %T28_X %T28_Y %T28_Z
%T28_W %T29_X %T29_Y %T29_Z %T29_W %T30_X %T30_Y %T30_Z %T30_W %T31_X %T31_Y
%T31_Z %T31_W %T32_X %T32_Y %T32_Z %T32_W %T33_X %T33_Y %T33_Z %T33_W %T34_X
%T34_Y %T34_Z %T34_W %T35_X %T35_Y %T35_Z
 %T35_W %T36_X %T36_Y %T36_Z %T36_W %T37_X %T37_Y %T37_Z %T37_W %T38_X %T38_Y
%T38_Z %T38_W %T39_X %T39_Y %T39_Z %T39_W %T40_X %T40_Y %T40_Z %T40_W %T41_X
%T41_Y %T41_Z %T41_W %T42_X %T42_Y %T42_Z %T42_W %T43_X %T43_Y %T43_Z %T43_W
%T44_X %T44_Y %T44_Z %T44_W %T45_X %T45_Y %T45_Z %T45_W %T46_X %T46_Y %T46_Z
%T46_W %T47_X %T47_Y %T47_Z %T47_W %T48_X %T48_Y %T48_Z %T48_W %T49_X %T49_Y
%T49_Z %T49_W %T50_X %T50_Y %T50_Z %T50_W %T51_X %T51_Y %T51_Z %T51_W %T52_X
%T52_Y %T52_Z %T52_W %T53_X %T53_Y %T53_Z %T53_W %T54_X %T54_Y %T54_Z %T54_W
%T55_X %T55_Y %T55_Z %T55_W %T56_X %T56_Y %T56_Z %T56_W %T57_X %T57_Y %T57_Z
%T57_W %T58_X %T58_Y %T58_Z %T58_W %T59_X %T59_Y %T59_Z %T59_W %T60_X %T60_Y
%T60_Z %T60_W %T61_X %T61_Y %T61_Z %T61_W %T62_X %T62_Y %T62_Z %T62_W %T63_X
%T63_Y %T63_Z %T63_W %T64_X %T64_Y %T64_Z %T64_W %T65_X %T65_Y %T65_Z %T65_W
%T66_X %T66_Y %T66_Z %T66_W %T67_X %T67_Y %T67_Z %T67_W %T68_X %T68_Y %T68_Z
%T68_W %T69_X %T69_Y %T69_Z %T69_W %T70_X
 %T70_Y %T70_Z %T70_W %T71_X %T71_Y %T71_Z %T71_W %T72_X %T72_Y %T72_Z %T72_W
%T73_X %T73_Y %T73_Z %T73_W %T74_X %T74_Y %T74_Z %T74_W %T75_X %T75_Y %T75_Z
%T75_W %T76_X %T76_Y %T76_Z %T76_W %T77_X %T77_Y %T77_Z %T77_W %T78_X %T78_Y
%T78_Z %T78_W %T79_X %T79_Y %T79_Z %T79_W %T80_X %T80_Y %T80_Z %T80_W %T81_X
%T81_Y %T81_Z %T81_W %T82_X %T82_Y %T82_Z %T82_W %T83_X %T83_Y %T83_Z %T83_W
%T84_X %T84_Y %T84_Z %T84_W %T85_X %T85_Y %T85_Z %T85_W %T86_X %T86_Y %T86_Z
%T86_W %T87_X %T87_Y %T87_Z %T87_W %T88_X %T88_Y %T88_Z %T88_W %T89_X %T89_Y
%T89_Z %T89_W %T90_X %T90_Y %T90_Z %T90_W %T91_X %T91_Y %T91_Z %T91_W %T92_X
%T92_Y %T92_Z %T92_W %T93_X %T93_Y %T93_Z %T93_W %T94_X %T94_Y %T94_Z %T94_W
%T95_X %T95_Y %T95_Z %T95_W %T96_X %T96_Y %T96_Z %T96_W %T97_X %T97_Y %T97_Z
%T97_W %T98_X %T98_Y %T98_Z %T98_W %T99_X %T99_Y %T99_Z %T99_W %T100_X %T100_Y
%T100_Z %T100_W %T101_X %T101_Y %T101_Z %T101_W %T102_X %T102_Y %T102_Z %T102_W
%T103_X %T103_Y %T103_Z %T103_W
 %T104_X %T104_Y %T104_Z %T104_W %T105_X %T105_Y %T105_Z %T105_W %T106_X %T106_Y
%T106_Z %T106_W %T107_X %T107_Y %T107_Z %T107_W %T108_X %T108_Y %T108_Z %T108_W
%T109_X %T109_Y %T109_Z %T109_W %T110_X %T110_Y %T110_Z %T110_W %T111_X %T111_Y
%T111_Z %T111_W %T112_X %T112_Y %T112_Z %T112_W %T113_X %T113_Y %T113_Z %T113_W
%T114_X %T114_Y %T114_Z %T114_W %T115_X %T115_Y %T115_Z %T115_W %T116_X %T116_Y
%T116_Z %T116_W %T117_X %T117_Y %T117_Z %T117_W %T118_X %T118_Y %T118_Z %T118_W
%T119_X %T119_Y %T119_Z %T119_W %T120_X %T120_Y %T120_Z %T120_W %T121_X %T121_Y
%T121_Z %T121_W %T122_X %T122_Y %T122_Z %T122_W %T123_X %T123_Y %T123_Z %T123_W
%T124_X %T124_Y %T124_Z %T124_W %T125_X %T125_Y %T125_Z %T125_W %T126_X %T126_Y
%T126_Z %T126_W %T127_X %T127_Y %T127_Z %T127_W %ArrayBase448 %ArrayBase449
%ArrayBase450 %ArrayBase451 %ArrayBase452 %ArrayBase453 %ArrayBase454
%ArrayBase455 %ArrayBase456 %ArrayBase457 %ArrayBase458 %ArrayBase459
%ArrayBase460 %ArrayBase461
 %ArrayBase462 %ArrayBase463 %ArrayBase464 ]
assigning %vreg49 to %T3_X: T3_X

selectOrSplit R600_Reg32:%vreg30 [512r,544r:0)  0 at 512r
assigning %vreg30 to %T3_Y: T3_Y

selectOrSplit R600_Reg32:%vreg38 [1072r,1088r:0)  0 at 1072r
assigning %vreg38 to %T3_Y: T3_Y
********** REWRITE VIRTUAL REGISTERS **********
********** Function: main
********** REGISTER MAP **********
[%vreg1 -> %T1_XYZW] R600_Reg128
[%vreg27 -> %T2_XYZW] R600_Reg128
[%vreg30 -> %T3_Y] R600_Reg32
[%vreg38 -> %T3_Y] R600_Reg32
[%vreg49 -> %T3_X] R600_Reg32

0BBB#0: derived from LLVM BB %0
    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%vreg1:sel_w<def,read-undef> = COPY %T1_W; R600_Reg128:%vreg1
32B%vreg1:sel_z<def> = COPY %T1_Z; R600_Reg128:%vreg1
48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27
192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
    Successors according to CFG: BB#1> %T1_W<def> = COPY %T1_W, %T1_XYZW<imp-def>Identity copy: %T1_W<def> = KILL %T1_W,
%T1_XYZW<imp-def>> %T1_Z<def> = COPY %T1_Z, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>Identity copy: %T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>> %T1_Y<def> = COPY %T1_Y, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>Identity copy: %T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>> %T1_X<def> = COPY %T1_X, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>Identity copy: %T1_X<def> = KILL %T1_X, %T1_XYZW<imp-use,kill>,
%T1_XYZW<imp-def>> %T2_X<def> = COPY %C1_X, %T2_XYZW<imp-def>
> %T2_Y<def> = COPY %C1_Y, %T2_XYZW<imp-use,kill>,
%T2_XYZW<imp-def>
> %T2_Z<def> = COPY %C1_Z, %T2_XYZW<imp-use,kill>,
%T2_XYZW<imp-def>
> %T2_W<def> = COPY %C1_W, %T2_XYZW<imp-use,kill>,
%T2_XYZW<imp-def>
> %T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0448BBB#1: derived from LLVM BB %25
    Live Ins: %T1_XYZW %T2_XYZW %T3_X
    Predecessors according to CFG: BB#0 BB#3
512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0,
0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16;
R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
    Successors according to CFG: BB#2(4) BB#3(124)> %T3_Y<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %T3_X, 0, 0,
0, 1, pred:%PRED_SEL_OFF, 0
> %PREDICATE_BIT<def> = PRED_X %T3_Y<kill>, 152, 16
> JUMP <BB#3>, pred:%PREDICATE_BIT
> JUMP <BB#2>, pred:%noreg592BBB#2: derived from LLVM BB %31
    Live Ins: %T1_XYZW %T2_XYZW
    Predecessors according to CFG: BB#1
624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>,
%T1_X<imp-use>, %T2_W<imp-use>, %T2_Z<imp-use>,
%T2_Y<imp-use>, %T2_X<imp-use>> %T2_X<def> = COPY %T2_X
Deleting identity copy.> %T2_Y<def> = COPY %T2_Y
Deleting identity copy.> %T2_Z<def> = COPY %T2_Z
Deleting identity copy.> %T2_W<def> = COPY %T2_W
Deleting identity copy.> %T1_X<def> = COPY %T1_X
Deleting identity copy.> %T1_Y<def> = COPY %T1_Y
Deleting identity copy.> %T1_Z<def> = COPY %T1_Z
Deleting identity copy.> %T1_W<def> = COPY %T1_W
Deleting identity copy.> RETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>,
%T1_X<imp-use>, %T2_W<imp-use>, %T2_Z<imp-use>,
%T2_Y<imp-use>, %T2_X<imp-use>880BBB#3: derived from LLVM BB %41
    Live Ins: %T1_XYZW %T2_XYZW %T3_X
    Predecessors according to CFG: BB#1
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49<kill>, 0, 0,
0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg49,%vreg38
1152BJUMP <BB#1>, pred:%noreg
    Successors according to CFG: BB#1> %T3_Y<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1
> %T3_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T3_X<kill>, 0, 0, 0,
%T3_Y<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0
> JUMP <BB#1>, pred:%noreg

Vincent Lejeune

2012-Oct-25 16:14 UTC

head link

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

When examining the debug output of regalloc, it seems that joining 32bits reg
also joins 128 parent reg.

If I look at the :
%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6

instructions ; it gets joined to :
928B%vreg34<def> = COPY %vreg48:sel_y; 

when vreg6 and vreg48 are joined. It's right.

But joining the following copy 

912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;
R600_Reg128:%vreg32,%vreg48

updates it to 
928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg32

which is wrong. vreg32:sel_y is undef.

Regards,
Vincent


----- Mail original -----> De : Vincent Lejeune <vljn at ovi.com>
> À : Ivan Llopard <ivanllopard at gmail.com>
> Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu>
> Envoyé le : Jeudi 25 octobre 2012 17h54
> Objet : Re: [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
> 
> 
> 
>> 
>>  PHIElim and TwoAddress passes leave SSA form.
>>  May be a missed something in your code but %vreg48 seems to be there 
>>  after PHI elimination. PHIElim tags those kind of registers as being 
>>  PHIJoin regs, updating LiveVariables pass, so the regcoalescer is
aware
>>  of them (some SSA info is still alive but the reg coalescer will 
>>  invalidate that information after joining intervals). PHIJoin regs 
>>  doesn't get modified by any other instruction than copies.
>>  Anyway, IMHO if your code is faulty there should be a bug somewhere
else.
>> 
> 
> 
> It seems the PhiElim is working correctly, the output of
--debug-only=regalloc
> shows that %vreg48 is a phi-join register, and intervals looks correct to
me :
> 
> ********** COMPUTING LIVE INTERVALS **********
> ********** Function: main
> BB#0:# derived from 
> 16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
> register: %vreg17 +[16r,352r:0)
> 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; 
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; 
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> register: %vreg21 +[128r,176r:0)
> 144B%vreg23<def> = COPY %vreg19<kill>;
R600_Reg128:%vreg23,%vreg19
> register: %vreg23 +[144r,224r:0)
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>;
R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> register: %vreg23 replace range with [144r,160r:1) RESULT: 
> [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
> 176B%vreg24<def> = COPY %vreg21<kill>;
R600_Reg128:%vreg24,%vreg21
> register: %vreg24 +[176r,256r:0)
> 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 
> R600_Reg32:%vreg2
> register: %vreg24 replace range with [176r,192r:1) RESULT: 
> [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +[208r,272r:0)
> 224B%vreg26<def> = COPY %vreg23<kill>;
R600_Reg128:%vreg26,%vreg23
> register: %vreg26 +[224r,336r:0)
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>;
R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> register: %vreg26 replace range with [224r,240r:1) RESULT: 
> [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
> 256B%vreg27<def> = COPY %vreg24<kill>;
R600_Reg128:%vreg27,%vreg24
> register: %vreg27 +[256r,304r:0)
> 272B%vreg27:sel_z<def> = COPY %vreg25<kill>;
R600_Reg128:%vreg27
> R600_Reg32:%vreg25
> register: %vreg27 replace range with [256r,272r:1) RESULT: 
> [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
> 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> register: %vreg28 +[288r,320r:0)
> 304B%vreg3<def> = COPY %vreg27<kill>;
R600_Reg128:%vreg3,%vreg27
> register: %vreg3 +[304r,416r:0)
> 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 
> R600_Reg32:%vreg28
> register: %vreg3 replace range with [304r,320r:1) RESULT: 
> [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
> 336B%vreg1<def> = COPY %vreg26<kill>;
R600_Reg128:%vreg1,%vreg26
> register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0)
+[592B,832r:0)
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 
> R600_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT: 
> [336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
> 416B%vreg48<def> = COPY %vreg3<kill>;
R600_Reg128:%vreg48,%vreg3
> register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
> 432B%vreg49<def> = COPY %vreg13<kill>;
R600_Reg32:%vreg49,%vreg13
> register: %vreg49 +[432r,448B:0) phi-join +[448B,496r:1)
> BB#1:# derived from 
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> register: %vreg5 +[464r,592B:0) +[880B,992r:0)
> 480B%vreg6<def> = COPY %vreg48<kill>;
R600_Reg128:%vreg6,%vreg48
> register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0,
%vreg7, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
> register: %vreg29 +[512r,528r:0)
> 528B%vreg30<def> = COPY %vreg29<kill>;
R600_Reg32:%vreg30,%vreg29
> register: %vreg30 +[528r,544r:0)
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; 
> R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
> BB#2:# derived from 
> 608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg6
> register: %vreg39 +[608r,624r:0)
> 624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39
> 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg6
> register: %vreg40 +[640r,656r:0)
> 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40
> 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg6
> register: %vreg41 +[672r,688r:0)
> 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41
> 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 
> R600_Reg128:%vreg6
> register: %vreg42 +[704r,720r:0)
> 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
> 736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 
> R600_Reg128:%vreg1
> register: %vreg43 +[736r,752r:0)
> 752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
> 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 
> R600_Reg128:%vreg1
> register: %vreg44 +[768r,784r:0)
> 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
> 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 
> R600_Reg128:%vreg1
> register: %vreg45 +[800r,816r:0)
> 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
> 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 
> R600_Reg128:%vreg1
> register: %vreg46 +[832r,848r:0)
> 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
> 864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, 
> %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>,
%T2_W<imp-use,kill>,
> %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>,
%T2_X<imp-use,kill>
> BB#3:# derived from 
> 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 
> R600_Reg128:%vreg6
> register: %vreg31 +[896r,912r:0)
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; 
> R600_Reg128:%vreg32 R600_Reg32:%vreg31
> register: %vreg32 +[912r,944r:0)
> 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg6
> register: %vreg34 +[928r,960r:0)
> 944B%vreg35<def> = COPY %vreg32<kill>;
R600_Reg128:%vreg35,%vreg32
> register: %vreg35 +[944r,976r:0)
> 960B%vreg35:sel_y<def> = COPY %vreg34<kill>;
R600_Reg128:%vreg35
> R600_Reg32:%vreg34
> register: %vreg35 replace range with [944r,960r:1) RESULT: 
> [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
> 976B%vreg36<def> = COPY %vreg35<kill>;
R600_Reg128:%vreg36,%vreg35
> register: %vreg36 +[976r,1024r:0)
> 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36
> R600_Reg32:%vreg5
> register: %vreg36 replace range with [976r,992r:1) RESULT: 
> [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
> 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg6
> register: %vreg37 +[1008r,1040r:0)
> 1024B%vreg10<def> = COPY %vreg36<kill>;
R600_Reg128:%vreg10,%vreg36
> register: %vreg10 +[1024r,1120r:0)
> 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>;
R600_Reg128:%vreg10
> R600_Reg32:%vreg37
> register: %vreg10 replace range with [1024r,1040r:1) RESULT: 
> [1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
> 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 
> R600_Reg128:%vreg6
> register: %vreg9 +[1056r,1104r:0)
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> register: %vreg38 +[1072r,1088r:0)
> 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0,
0, 0,
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg11,%vreg7,%vreg38
> register: %vreg11 +[1088r,1136r:0)
> 1104B%vreg47<def> = COPY %vreg9<kill>;
R600_Reg32:%vreg47,%vreg9
> register: %vreg47 phi-join +[1104r,1168B:2)
> 1120B%vreg48<def> = COPY %vreg10<kill>;
R600_Reg128:%vreg48,%vreg10
> register: %vreg48 phi-join +[1120r,1168B:2)
> 1136B%vreg49<def> = COPY %vreg11<kill>;
R600_Reg32:%vreg49,%vreg11
> register: %vreg49 phi-join +[1136r,1168B:2)
> 1152BJUMP <BB#1>, pred:%noreg
> Computing live-in reg-units in ABI blocks.
> 0BBB#0 T1_X#0 T1_Y#0 T1_Z#0 T1_W#0
> Created 4 new intervals.
> ********** INTERVALS **********
> T1_W = [0B,16r:0)[848r,864r:1)  0 at 0B-phi 1 at 848r
> T1_X = [0B,64r:0)[752r,864r:1)  0 at 0B-phi 1 at 752r
> T1_Y = [0B,48r:0)[784r,864r:1)  0 at 0B-phi 1 at 784r
> T1_Z = [0B,32r:0)[816r,864r:1)  0 at 0B-phi 1 at 816r
> %vreg0 = [384r,592B:0)[880B,1168B:0)  0 at 384r
> %vreg1 = [336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
> %vreg2 = [112r,400r:0)  0 at 112r
> %vreg3 = [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
> %vreg5 = [464r,592B:0)[880B,992r:0)  0 at 464r
> %vreg6 = [480r,704r:0)[880B,1056r:0)  0 at 480r
> %vreg7 = [496r,592B:0)[880B,1088r:0)  0 at 496r
> %vreg9 = [1056r,1104r:0)  0 at 1056r
> %vreg10 = [1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
> %vreg11 = [1088r,1136r:0)  0 at 1088r
> %vreg13 = [368r,432r:0)  0 at 368r
> %vreg14 = [64r,96r:0)  0 at 64r
> %vreg15 = [48r,160r:0)  0 at 48r
> %vreg16 = [32r,240r:0)  0 at 32r
> %vreg17 = [16r,352r:0)  0 at 16r
> %vreg18 = [80r,128r:0)  0 at 80r
> %vreg19 = [96r,144r:0)  0 at 96r
> %vreg21 = [128r,176r:0)  0 at 128r
> %vreg23 = [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
> %vreg24 = [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
> %vreg25 = [208r,272r:0)  0 at 208r
> %vreg26 = [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
> %vreg27 = [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
> %vreg28 = [288r,320r:0)  0 at 288r
> %vreg29 = [512r,528r:0)  0 at 512r
> %vreg30 = [528r,544r:0)  0 at 528r
> %vreg31 = [896r,912r:0)  0 at 896r
> %vreg32 = [912r,944r:0)  0 at 912r
> %vreg34 = [928r,960r:0)  0 at 928r
> %vreg35 = [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
> %vreg36 = [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
> %vreg37 = [1008r,1040r:0)  0 at 1008r
> %vreg38 = [1072r,1088r:0)  0 at 1072r
> %vreg39 = [608r,624r:0)  0 at 608r
> %vreg40 = [640r,656r:0)  0 at 640r
> %vreg41 = [672r,688r:0)  0 at 672r
> %vreg42 = [704r,720r:0)  0 at 704r
> %vreg43 = [736r,752r:0)  0 at 736r
> %vreg44 = [768r,784r:0)  0 at 768r
> %vreg45 = [800r,816r:0)  0 at 800r
> %vreg46 = [832r,848r:0)  0 at 832r
> %vreg47 = [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at
448B-phi 2 at 1104r
> %vreg48 = [416r,448B:0)[448B,480r:1)[1120r,1168B:2)  0 at 416r 1 at
448B-phi 2 at 1120r
> %vreg49 = [432r,448B:0)[448B,496r:1)[1136r,1168B:2)  0 at 432r 1 at
448B-phi 2 at 1136r
> ********** MACHINEINSTRS **********
> # Machine code for function main: Post SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16,
%T1_W
> in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
> 
> 0BBB#0: derived from LLVM BB %0
>    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> 16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> 32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> 48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> 64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; 
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; 
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> 144B%vreg23<def> = COPY %vreg19<kill>;
R600_Reg128:%vreg23,%vreg19
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>;
R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> 176B%vreg24<def> = COPY %vreg21<kill>;
R600_Reg128:%vreg24,%vreg21
> 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 
> R600_Reg32:%vreg2
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> 224B%vreg26<def> = COPY %vreg23<kill>;
R600_Reg128:%vreg26,%vreg23
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>;
R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> 256B%vreg27<def> = COPY %vreg24<kill>;
R600_Reg128:%vreg27,%vreg24
> 272B%vreg27:sel_z<def> = COPY %vreg25<kill>;
R600_Reg128:%vreg27
> R600_Reg32:%vreg25
> 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> 304B%vreg3<def> = COPY %vreg27<kill>;
R600_Reg128:%vreg3,%vreg27
> 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 
> R600_Reg32:%vreg28
> 336B%vreg1<def> = COPY %vreg26<kill>;
R600_Reg128:%vreg1,%vreg26
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 
> R600_TReg32:%vreg17
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> 416B%vreg48<def> = COPY %vreg3<kill>;
R600_Reg128:%vreg48,%vreg3
> 432B%vreg49<def> = COPY %vreg13<kill>;
R600_Reg32:%vreg49,%vreg13
>    Successors according to CFG: BB#1
> 
> 448BBB#1: derived from LLVM BB %25
>    Predecessors according to CFG: BB#0 BB#3
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> 480B%vreg6<def> = COPY %vreg48<kill>;
R600_Reg128:%vreg6,%vreg48
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0,
%vreg7, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
> 528B%vreg30<def> = COPY %vreg29<kill>;
R600_Reg32:%vreg30,%vreg29
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; 
> R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
>    Successors according to CFG: BB#2(4) BB#3(124)
> 
> 592BBB#2: derived from LLVM BB %31
>    Predecessors according to CFG: BB#1
> 608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg6
> 624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39
> 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg6
> 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40
> 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg6
> 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41
> 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 
> R600_Reg128:%vreg6
> 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
> 736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 
> R600_Reg128:%vreg1
> 752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
> 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 
> R600_Reg128:%vreg1
> 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
> 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 
> R600_Reg128:%vreg1
> 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
> 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 
> R600_Reg128:%vreg1
> 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
> 864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>,
%T1_Y<imp-use>,
> %T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>,
> %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
> 
> 880BBB#3: derived from LLVM BB %41
>    Predecessors according to CFG: BB#1
> 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 
> R600_Reg128:%vreg6
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; 
> R600_Reg128:%vreg32 R600_Reg32:%vreg31
> 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg6
> 944B%vreg35<def> = COPY %vreg32<kill>;
R600_Reg128:%vreg35,%vreg32
> 960B%vreg35:sel_y<def> = COPY %vreg34<kill>;
R600_Reg128:%vreg35
> R600_Reg32:%vreg34
> 976B%vreg36<def> = COPY %vreg35<kill>;
R600_Reg128:%vreg36,%vreg35
> 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36
> R600_Reg32:%vreg5
> 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg6
> 1024B%vreg10<def> = COPY %vreg36<kill>;
R600_Reg128:%vreg10,%vreg36
> 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>;
R600_Reg128:%vreg10
> R600_Reg32:%vreg37
> 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 
> R600_Reg128:%vreg6
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0,
0, 0,
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg11,%vreg7,%vreg38
> 1104B%vreg47<def> = COPY %vreg9<kill>;
R600_Reg32:%vreg47,%vreg9
> 1120B%vreg48<def> = COPY %vreg10<kill>;
R600_Reg128:%vreg48,%vreg10
> 1136B%vreg49<def> = COPY %vreg11<kill>;
R600_Reg32:%vreg49,%vreg11
> 1152BJUMP <BB#1>, pred:%noreg
>    Successors according to CFG: BB#1
> 
> # End machine code for function main.
> 
> ********** SIMPLE REGISTER COALESCING **********
> ********** Function: main
> ********** JOINING INTERVALS ***********
> :
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> Considering merging to R600_Reg32 with %vreg47 in %vreg5
> RHS = %vreg5 [464r,592B:0)[880B,992r:0)  0 at 464r
> LHS = %vreg47 [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at
448B-phi
> 2 at 1104r
> merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
> erased:464r%vreg5<def> = COPY %vreg47<kill>; 
> R600_Reg32:%vreg5,%vreg47
> AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z
%T1_W
> %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W
%T5_X
> %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X
%T8_Y
> %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X
%T11_Y
> %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W
%T14_X
> %T14_Y %T14_Z %T14_W %T15_X %T15_Y %T15_Z %T15_W %T16_X %T16_Y %T16_Z
%T16_W
> %T17_X %T17_Y %T17_Z %T17_W %T18_X %T18_Y %T18_Z %T18_W %T19_X %T19_Y
%T19_Z
> %T19_W %T20_X %T20_Y %T20_Z %T20_W %T21_X %T21_Y %T21_Z %T21_W %T22_X
%T22_Y
> %T22_Z %T22_W %T23_X %T23_Y %T23_Z %T23_W %T24_X %T24_Y %T24_Z %T24_W
%T25_X
> %T25_Y %T25_Z %T25_W %T26_X %T26_Y %T26_Z %T26_W %T27_X %T27_Y %T27_Z
%T27_W
> %T28_X %T28_Y %T28_Z %T28_W %T29_X %T29_Y %T29_Z %T29_W %T30_X %T30_Y
%T30_Z
> %T30_W %T31_X %T31_Y %T31_Z %T31_W %T32_X %T32_Y %T32_Z %T32_W %T33_X
%T33_Y
> %T33_Z %T33_W %T34_X %T34_Y %T34_Z
> %T34_W %T35_X %T35_Y %T35_Z %T35_W %T36_X %T36_Y %T36_Z %T36_W %T37_X
%T37_Y
> %T37_Z %T37_W %T38_X %T38_Y %T38_Z %T38_W %T39_X %T39_Y %T39_Z %T39_W
%T40_X
> %T40_Y %T40_Z %T40_W %T41_X %T41_Y %T41_Z %T41_W %T42_X %T42_Y %T42_Z
%T42_W
> %T43_X %T43_Y %T43_Z %T43_W %T44_X %T44_Y %T44_Z %T44_W %T45_X %T45_Y
%T45_Z
> %T45_W %T46_X %T46_Y %T46_Z %T46_W %T47_X %T47_Y %T47_Z %T47_W %T48_X
%T48_Y
> %T48_Z %T48_W %T49_X %T49_Y %T49_Z %T49_W %T50_X %T50_Y %T50_Z %T50_W
%T51_X
> %T51_Y %T51_Z %T51_W %T52_X %T52_Y %T52_Z %T52_W %T53_X %T53_Y %T53_Z
%T53_W
> %T54_X %T54_Y %T54_Z %T54_W %T55_X %T55_Y %T55_Z %T55_W %T56_X %T56_Y
%T56_Z
> %T56_W %T57_X %T57_Y %T57_Z %T57_W %T58_X %T58_Y %T58_Z %T58_W %T59_X
%T59_Y
> %T59_Z %T59_W %T60_X %T60_Y %T60_Z %T60_W %T61_X %T61_Y %T61_Z %T61_W
%T62_X
> %T62_Y %T62_Z %T62_W %T63_X %T63_Y %T63_Z %T63_W %T64_X %T64_Y %T64_Z
%T64_W
> %T65_X %T65_Y %T65_Z %T65_W %T66_X %T66_Y %T66_Z %T66_W %T67_X %T67_Y
%T67_Z
> %T67_W %T68_X %T68_Y %T68_Z %T68_W %T69_X
> %T69_Y %T69_Z %T69_W %T70_X %T70_Y %T70_Z %T70_W %T71_X %T71_Y %T71_Z
%T71_W
> %T72_X %T72_Y %T72_Z %T72_W %T73_X %T73_Y %T73_Z %T73_W %T74_X %T74_Y
%T74_Z
> %T74_W %T75_X %T75_Y %T75_Z %T75_W %T76_X %T76_Y %T76_Z %T76_W %T77_X
%T77_Y
> %T77_Z %T77_W %T78_X %T78_Y %T78_Z %T78_W %T79_X %T79_Y %T79_Z %T79_W
%T80_X
> %T80_Y %T80_Z %T80_W %T81_X %T81_Y %T81_Z %T81_W %T82_X %T82_Y %T82_Z
%T82_W
> %T83_X %T83_Y %T83_Z %T83_W %T84_X %T84_Y %T84_Z %T84_W %T85_X %T85_Y
%T85_Z
> %T85_W %T86_X %T86_Y %T86_Z %T86_W %T87_X %T87_Y %T87_Z %T87_W %T88_X
%T88_Y
> %T88_Z %T88_W %T89_X %T89_Y %T89_Z %T89_W %T90_X %T90_Y %T90_Z %T90_W
%T91_X
> %T91_Y %T91_Z %T91_W %T92_X %T92_Y %T92_Z %T92_W %T93_X %T93_Y %T93_Z
%T93_W
> %T94_X %T94_Y %T94_Z %T94_W %T95_X %T95_Y %T95_Z %T95_W %T96_X %T96_Y
%T96_Z
> %T96_W %T97_X %T97_Y %T97_Z %T97_W %T98_X %T98_Y %T98_Z %T98_W %T99_X
%T99_Y
> %T99_Z %T99_W %T100_X %T100_Y %T100_Z %T100_W %T101_X %T101_Y %T101_Z
%T101_W
> %T102_X %T102_Y %T102_Z %T102_W %T103_X
> %T103_Y %T103_Z %T103_W %T104_X %T104_Y %T104_Z %T104_W %T105_X %T105_Y
%T105_Z
> %T105_W %T106_X %T106_Y %T106_Z %T106_W %T107_X %T107_Y %T107_Z %T107_W
%T108_X
> %T108_Y %T108_Z %T108_W %T109_X %T109_Y %T109_Z %T109_W %T110_X %T110_Y
%T110_Z
> %T110_W %T111_X %T111_Y %T111_Z %T111_W %T112_X %T112_Y %T112_Z %T112_W
%T113_X
> %T113_Y %T113_Z %T113_W %T114_X %T114_Y %T114_Z %T114_W %T115_X %T115_Y
%T115_Z
> %T115_W %T116_X %T116_Y %T116_Z %T116_W %T117_X %T117_Y %T117_Z %T117_W
%T118_X
> %T118_Y %T118_Z %T118_W %T119_X %T119_Y %T119_Z %T119_W %T120_X %T120_Y
%T120_Z
> %T120_W %T121_X %T121_Y %T121_Z %T121_W %T122_X %T122_Y %T122_Z %T122_W
%T123_X
> %T123_Y %T123_Z %T123_W %T124_X %T124_Y %T124_Z %T124_W %T125_X %T125_Y
%T125_Z
> %T125_W %T126_X %T126_Y %T126_Z %T126_W %T127_X %T127_Y %T127_Z %T127_W 
> %ArrayBase448 %ArrayBase449 %ArrayBase450 %ArrayBase451 %ArrayBase452 
> %ArrayBase453 %ArrayBase454 %ArrayBase455 %ArrayBase456 %ArrayBase457 
> %ArrayBase458 %ArrayBase459
> %ArrayBase460 %ArrayBase461 %ArrayBase462 %ArrayBase463 %ArrayBase464 ]
> updated: 992B%vreg36:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg36 
> R600_Reg32:%vreg47
> Joined. Result =
%vreg47[400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)
>  0 at 400r 1 at 448B-phi 2 at 1104r
> 480B%vreg6<def> = COPY %vreg48<kill>;
R600_Reg128:%vreg6,%vreg48
> Considering merging to R600_Reg128 with %vreg48 in %vreg6
> RHS = %vreg6 [480r,704r:0)[880B,1056r:0)  0 at 480r
> LHS = %vreg48 [416r,448B:0)[448B,480r:1)[1120r,1168B:2)  0 at 416r 1 at
448B-phi
> 2 at 1120r
> merge %vreg6:0 at 480r into %vreg48:1 at 448B --> @448B
> erased:480r%vreg6<def> = COPY %vreg48<kill>; 
> R600_Reg128:%vreg6,%vreg48
> AllocationOrder(R600_Reg128) = [ %T0_XYZW %T1_XYZW %T2_XYZW %T3_XYZW
%T4_XYZW
> %T5_XYZW %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW 
> %T13_XYZW %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW
%T20_XYZW
> %T21_XYZW %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW
%T28_XYZW
> %T29_XYZW %T30_XYZW %T31_XYZW %T32_XYZW %T33_XYZW %T34_XYZW %T35_XYZW
%T36_XYZW
> %T37_XYZW %T38_XYZW %T39_XYZW %T40_XYZW %T41_XYZW %T42_XYZW %T43_XYZW
%T44_XYZW
> %T45_XYZW %T46_XYZW %T47_XYZW %T48_XYZW %T49_XYZW %T50_XYZW %T51_XYZW
%T52_XYZW
> %T53_XYZW %T54_XYZW %T55_XYZW %T56_XYZW %T57_XYZW %T58_XYZW %T59_XYZW
%T60_XYZW
> %T61_XYZW %T62_XYZW %T63_XYZW %T64_XYZW %T65_XYZW %T66_XYZW %T67_XYZW
%T68_XYZW
> %T69_XYZW %T70_XYZW %T71_XYZW %T72_XYZW %T73_XYZW %T74_XYZW %T75_XYZW
%T76_XYZW
> %T77_XYZW %T78_XYZW %T79_XYZW %T80_XYZW %T81_XYZW %T82_XYZW %T83_XYZW
%T84_XYZW
> %T85_XYZW %T86_XYZW %T87_XYZW %T88_XYZW %T89_XYZW %T90_XYZW %T91_XYZW
%T92_XYZW
> %T93_XYZW
> %T94_XYZW %T95_XYZW %T96_XYZW %T97_XYZW %T98_XYZW %T99_XYZW %T100_XYZW 
> %T101_XYZW %T102_XYZW %T103_XYZW %T104_XYZW %T105_XYZW %T106_XYZW
%T107_XYZW
> %T108_XYZW %T109_XYZW %T110_XYZW %T111_XYZW %T112_XYZW %T113_XYZW
%T114_XYZW
> %T115_XYZW %T116_XYZW %T117_XYZW %T118_XYZW %T119_XYZW %T120_XYZW
%T121_XYZW
> %T122_XYZW %T123_XYZW %T124_XYZW %T125_XYZW %T126_XYZW %T127_XYZW ]
> updated: 896B%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31 
> R600_Reg128:%vreg48
> updated: 928B%vreg34<def> = COPY %vreg48:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg48
> updated: 1008B%vreg37<def> = COPY %vreg48:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg48
> updated: 1056B%vreg9<def> = COPY %vreg48:sel_z; R600_Reg32:%vreg9 
> R600_Reg128:%vreg48
> updated: 608B%vreg39<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg48
> updated: 640B%vreg40<def> = COPY %vreg48:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg48
> updated: 672B%vreg41<def> = COPY %vreg48:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg48
> updated: 704B%vreg42<def> = COPY %vreg48:sel_w; R600_Reg32:%vreg42 
> R600_Reg128:%vreg48
> Joined. Result =
%vreg48[416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)
>  0 at 416r 1 at 448B-phi 2 at 1120r
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> Considering merging to R600_Reg32 with %vreg49 in %vreg7
> RHS = %vreg7 [496r,592B:0)[880B,1088r:0)  0 at 496r
> LHS = %vreg49 [432r,448B:0)[448B,496r:1)[1136r,1168B:2)  0 at 432r 1 at
448B-phi
> 2 at 1136r
> merge %vreg7:0 at 496r into %vreg49:1 at 448B --> @448B
> erased:496r%vreg7<def> = COPY %vreg49<kill>; 
> R600_Reg32:%vreg7,%vreg49
> updated: 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0,
0,
> %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg29,%vreg0,%vreg49
> updated: 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0,
0,
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg11,%vreg49,%vreg38
> Joined. Result =
%vreg49[432r,448B:0)[448B,592B:1)[880B,1088r:1)[1136r,1168B:2)
>  0 at 432r 1 at 448B-phi 2 at 1136r
> 528B%vreg30<def> = COPY %vreg29<kill>;
R600_Reg32:%vreg30,%vreg29
> Considering merging to R600_Reg32 with %vreg29 in %vreg30
> RHS = %vreg29 [512r,528r:0)  0 at 512r
> LHS = %vreg30 [528r,544r:0)  0 at 528r
> merge %vreg30:0 at 528r into %vreg29:0 at 512r --> @512r
> erased:528r%vreg30<def> = COPY %vreg29<kill>; 
> R600_Reg32:%vreg30,%vreg29
> updated: 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0,
0,
> %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg30,%vreg0,%vreg49
> Joined. Result = %vreg30[512r,544r:0)  0 at 512r
> :
> 896B%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31 
> R600_Reg128:%vreg48
> Considering merging to R600_Reg128 with %vreg31 in %vreg48:sel_x
> RHS = %vreg31 [896r,912r:0)  0 at 896r
> LHS = %vreg48 [416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)  0 at
416r
> 1 at 448B-phi 2 at 1120r
> merge %vreg31:0 at 896r into %vreg48:1 at 448B --> @448B
> erased:896r%vreg31<def> = COPY %vreg48:sel_x; R600_Reg32:%vreg31 
> R600_Reg128:%vreg48
> updated: 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; 
> R600_Reg128:%vreg32,%vreg48
> Joined. Result =
%vreg48[416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)
>  0 at 416r 1 at 448B-phi 2 at 1120r
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; 
> R600_Reg128:%vreg32,%vreg48
> Considering merging to R600_Reg128 with %vreg48 in %vreg32
> RHS = %vreg48 [416r,448B:0)[448B,704r:1)[880B,1056r:1)[1120r,1168B:2)  0 at
416r
> 1 at 448B-phi 2 at 1120r
> LHS = %vreg32 [912r,944r:0)  0 at 912r
> merge %vreg32:0 at 912r into %vreg48:1 at 448B --> @448B
> erased:912r%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; 
> R600_Reg128:%vreg32,%vreg48
> updated: 416B%vreg32<def> = COPY %vreg3<kill>; 
> R600_Reg128:%vreg32,%vreg3
> updated: 1120B%vreg32<def> = COPY %vreg10<kill>; 
> R600_Reg128:%vreg32,%vreg10
> updated: 928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg32
> updated: 1008B%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg32
> updated: 1056B%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9 
> R600_Reg128:%vreg32
> updated: 608B%vreg39<def> = COPY %vreg32:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg32
> updated: 640B%vreg40<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg32
> updated: 672B%vreg41<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg32
> updated: 704B%vreg42<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg42 
> R600_Reg128:%vreg32
> Joined. Result =
%vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
>  0 at 448B-phi 1 at 416r 2 at 1120r
> 928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg32
> Considering merging to R600_Reg128 with %vreg34 in %vreg32:sel_y
> RHS = %vreg34 [928r,960r:0)  0 at 928r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg34:0 at 928r into %vreg32:0 at 448B --> @448B
> erased:928r%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 
> R600_Reg128:%vreg32
> updated: 960B%vreg35:sel_y<def> = COPY %vreg32:sel_y; 
> R600_Reg128:%vreg35,%vreg32
> Joined. Result =
%vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
>  0 at 448B-phi 1 at 416r 2 at 1120r
> 944B%vreg35<def> = COPY %vreg32; R600_Reg128:%vreg35,%vreg32
> Considering merging to R600_Reg128 with %vreg32 in %vreg35
> RHS = %vreg35 [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg35:1 at 944r into %vreg32:0 at 448B --> @448B
> merge %vreg35:0 at 960r into %vreg32:0 at 448B --> @448B
> erased:960r%vreg35:sel_y<def> = COPY %vreg32:sel_y; 
> R600_Reg128:%vreg35,%vreg32
> erased:944r%vreg35<def> = COPY %vreg32; R600_Reg128:%vreg35,%vreg32
> updated: 976B%vreg36<def> = COPY %vreg32; R600_Reg128:%vreg36,%vreg32
> Joined. Result =
%vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
>  0 at 448B-phi 1 at 416r 2 at 1120r
> 976B%vreg36<def> = COPY %vreg32; R600_Reg128:%vreg36,%vreg32
> Considering merging to R600_Reg128 with %vreg32 in %vreg36
> RHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg36:1 at 976r into %vreg32:0 at 448B --> @448B
> conflict at %vreg36:0 at 992r
> taints local %vreg32:0 at 880B to 1056r
> tainted lanes used by: %vreg9<def> = COPY %vreg32:sel_z;
R600_Reg32:%vreg9
> R600_Reg128:%vreg32
> Interference!
> 992B%vreg36:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg36 
> R600_Reg32:%vreg47
> Considering merging to R600_Reg128 with %vreg47 in %vreg36:sel_z
> RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at
400r
> 1 at 448B-phi 2 at 1104r
> LHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
> merge %vreg36:0 at 992r into %vreg47:1 at 448B --> @448B
> interference at %vreg36:1 at 976r
> Interference!
> 1008B%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg32
> Considering merging to R600_Reg128 with %vreg37 in %vreg32:sel_w
> RHS = %vreg37 [1008r,1040r:0)  0 at 1008r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg37:0 at 1008r into %vreg32:0 at 448B --> @448B
> erased:1008r%vreg37<def> = COPY %vreg32:sel_w; R600_Reg32:%vreg37 
> R600_Reg128:%vreg32
> updated: 1040B%vreg10:sel_w<def> = COPY %vreg32:sel_w; 
> R600_Reg128:%vreg10,%vreg32
> Joined. Result =
%vreg32[416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2)
>  0 at 448B-phi 1 at 416r 2 at 1120r
> 1024B%vreg10<def> = COPY %vreg36<kill>;
R600_Reg128:%vreg10,%vreg36
> Considering merging to R600_Reg128 with %vreg36 in %vreg10
> RHS = %vreg36 [976r,992r:1)[992r,1024r:0)  0 at 992r 1 at 976r
> LHS = %vreg10 [1024r,1040r:1)[1040r,1120r:0)  0 at 1040r 1 at 1024r
> merge %vreg10:1 at 1024r into %vreg36:0 at 992r --> @992r
> erased:1024r%vreg10<def> = COPY %vreg36<kill>; 
> R600_Reg128:%vreg10,%vreg36
> updated: 976B%vreg10<def> = COPY %vreg32; R600_Reg128:%vreg10,%vreg32
> updated: 992B%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 
> R600_Reg32:%vreg47
> Joined. Result = %vreg10[976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at
976r
> 1 at 992r 2 at 1040r
> 1040B%vreg10:sel_w<def> = COPY %vreg32:sel_w;
R600_Reg128:%vreg10,%vreg32
> Considering merging to R600_Reg128 with %vreg32 in %vreg10
> RHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> LHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at
992r 2 at 1040r
> merge %vreg10:0 at 976r into %vreg32:0 at 448B --> @448B
> merge %vreg10:2 at 1040r into %vreg32:0 at 448B --> @448B
> merge %vreg32:2 at 1120r into %vreg10:2 at 1040r --> @448B
> conflict at %vreg10:1 at 992r
> taints local %vreg32:0 at 880B to 1056r
> tainted lanes used by: %vreg9<def> = COPY %vreg32:sel_z;
R600_Reg32:%vreg9
> R600_Reg128:%vreg32
> Interference!
> 1056B%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9 
> R600_Reg128:%vreg32
> Considering merging to R600_Reg128 with %vreg9 in %vreg32:sel_z
> RHS = %vreg9 [1056r,1104r:0)  0 at 1056r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1056r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg9:0 at 1056r into %vreg32:0 at 448B --> @448B
> erased:1056r%vreg9<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg9 
> R600_Reg128:%vreg32
> updated: 1104B%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 
> R600_Reg128:%vreg32
> Joined. Result =
%vreg32[416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2)
>  0 at 448B-phi 1 at 416r 2 at 1120r
> 1104B%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 
> R600_Reg128:%vreg32
> Considering merging to R600_Reg128 with %vreg47 in %vreg32:sel_z
> RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at
400r
> 1 at 448B-phi 2 at 1104r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> interference at %vreg32:1 at 416r
> Interference!
> 1120B%vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10
> Considering merging to R600_Reg128 with %vreg10 in %vreg32
> RHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at
992r 2 at 1040r
> LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2) 
>  0 at 448B-phi 1 at 416r 2 at 1120r
> merge %vreg10:0 at 976r into %vreg32:0 at 448B --> @448B
> merge %vreg10:2 at 1040r into %vreg32:0 at 448B --> @448B
> merge %vreg32:2 at 1120r into %vreg10:2 at 1040r --> @448B
> conflict at %vreg10:1 at 992r
> taints local %vreg32:0 at 880B to 1104r
> tainted lanes used by: %vreg47<def> = COPY %vreg32:sel_z; 
> R600_Reg32:%vreg47 R600_Reg128:%vreg32
> Extending: %vreg32   result = [416r,448B:1)[448B,704r:0)[880B,1168B:0) 
>  0 at 448B-phi 1 at 416r
> Shrink: [976r,992r:0)[992r,1040r:1)[1040r,1120r:2)  0 at 976r 1 at 992r 2
at 1040r
> Shrunk: [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at 992r 2
at 1040r
> Trivial!
> 1136B%vreg49<def> = COPY %vreg11<kill>;
R600_Reg32:%vreg49,%vreg11
> Considering merging to R600_Reg32 with %vreg11 in %vreg49
> RHS = %vreg11 [1088r,1136r:0)  0 at 1088r
> LHS = %vreg49 [432r,448B:0)[448B,592B:1)[880B,1088r:1)[1136r,1168B:2)  0 at
432r
> 1 at 448B-phi 2 at 1136r
> merge %vreg49:2 at 1136r into %vreg11:0 at 1088r --> @1088r
> erased:1136r%vreg49<def> = COPY %vreg11<kill>; 
> R600_Reg32:%vreg49,%vreg11
> updated: 1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0,
0,
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg49,%vreg38
> Joined. Result =
%vreg49[432r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)
>  0 at 432r 1 at 448B-phi 2 at 1088r
> :
> 16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> Considering merging %vreg17 with %T1_W
> Can only merge into reserved registers.
> 32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> Considering merging %vreg16 with %T1_Z
> Can only merge into reserved registers.
> 48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> Considering merging %vreg15 with %T1_Y
> Can only merge into reserved registers.
> 64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> Considering merging %vreg14 with %T1_X
> Can only merge into reserved registers.
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> Considering merging %vreg18 with %C1_X
> RHS = %vreg18 [80r,128r:0)  0 at 80r
> updated: 128B%vreg21:sel_x<def,read-undef> = COPY %C1_X; 
> R600_Reg128:%vreg21
> Joined. Result = %C1_X
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; 
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> Considering merging to R600_Reg128 with %vreg14 in %vreg19:sel_x
> RHS = %vreg14 [64r,96r:0)  0 at 64r
> LHS = %vreg19 [96r,144r:0)  0 at 96r
> merge %vreg19:0 at 96r into %vreg14:0 at 64r --> @64r
> erased:96r%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; 
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> updated: 64B%vreg19:sel_x<def,read-undef> = COPY %T1_X; 
> R600_Reg128:%vreg19
> Joined. Result = %vreg19[64r,144r:0)  0 at 64r
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> Considering merging %vreg2 with %C1_Y
> RHS = %vreg2 [112r,400r:0)  0 at 112r
> updated: 400B%vreg47<def> = COPY %C1_Y; R600_Reg32:%vreg47
> updated: 192B%vreg24:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg24
> Joined. Result = %C1_Y
> 128B%vreg21:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg21
> Not coalescable.
> 144B%vreg23<def> = COPY %vreg19; R600_Reg128:%vreg23,%vreg19
> Considering merging to R600_Reg128 with %vreg19 in %vreg23
> RHS = %vreg19 [64r,144r:0)  0 at 64r
> LHS = %vreg23 [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r
> merge %vreg23:1 at 144r into %vreg19:0 at 64r --> @64r
> erased:144r%vreg23<def> = COPY %vreg19; R600_Reg128:%vreg23,%vreg19
> updated: 64B%vreg23:sel_x<def,read-undef> = COPY %T1_X; 
> R600_Reg128:%vreg23
> Joined. Result = %vreg23[64r,160r:0)[160r,224r:1)  0 at 64r 1 at 160r
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>;
R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> Considering merging to R600_Reg128 with %vreg15 in %vreg23:sel_y
> RHS = %vreg15 [48r,160r:0)  0 at 48r
> LHS = %vreg23 [64r,160r:0)[160r,224r:1)  0 at 64r 1 at 160r
> merge %vreg23:1 at 160r into %vreg15:0 at 48r --> @48r
> pruned %vreg15 at 64r: [48r,64r:0)  0 at 48r
> pruned all of %vreg23 at 160r: [64r,160r:0)  0 at 64r 1 at 160r
> erased:160r%vreg23:sel_y<def> = COPY %vreg15<kill>; 
> R600_Reg128:%vreg23 R600_TReg32:%vreg15
> restoring liveness to 3 points: [48r,64r:0)[64r,160r:1)  0 at 48r 1 at 64r
> updated: 48B%vreg23:sel_y<def,read-undef> = COPY %T1_Y; 
> R600_Reg128:%vreg23
> Joined. Result = %vreg23[48r,64r:0)[64r,224r:1)  0 at 48r 1 at 64r
> 176B%vreg24<def> = COPY %vreg21<kill>;
R600_Reg128:%vreg24,%vreg21
> Considering merging to R600_Reg128 with %vreg21 in %vreg24
> RHS = %vreg21 [128r,176r:0)  0 at 128r
> LHS = %vreg24 [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r
> merge %vreg24:1 at 176r into %vreg21:0 at 128r --> @128r
> erased:176r%vreg24<def> = COPY %vreg21<kill>; 
> R600_Reg128:%vreg24,%vreg21
> updated: 128B%vreg24:sel_x<def,read-undef> = COPY %C1_X; 
> R600_Reg128:%vreg24
> Joined. Result = %vreg24[128r,192r:0)[192r,256r:1)  0 at 128r 1 at 192r
> 192B%vreg24:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg24
> Not coalescable.
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> Considering merging %vreg25 with %C1_Z
> RHS = %vreg25 [208r,272r:0)  0 at 208r
> updated: 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
> Joined. Result = %C1_Z
> 224B%vreg26<def> = COPY %vreg23; R600_Reg128:%vreg26,%vreg23
> Considering merging to R600_Reg128 with %vreg23 in %vreg26
> RHS = %vreg23 [48r,64r:0)[64r,224r:1)  0 at 48r 1 at 64r
> LHS = %vreg26 [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r
> merge %vreg26:1 at 224r into %vreg23:1 at 64r --> @64r
> erased:224r%vreg26<def> = COPY %vreg23; R600_Reg128:%vreg26,%vreg23
> updated: 48B%vreg26:sel_y<def,read-undef> = COPY %T1_Y; 
> R600_Reg128:%vreg26
> updated: 64B%vreg26:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg26
> Joined. Result = %vreg26[48r,64r:0)[64r,240r:1)[240r,336r:2)  0 at 48r 1 at
64r 2 at 240r
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>;
R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> Considering merging to R600_Reg128 with %vreg16 in %vreg26:sel_z
> RHS = %vreg16 [32r,240r:0)  0 at 32r
> LHS = %vreg26 [48r,64r:0)[64r,240r:1)[240r,336r:2)  0 at 48r 1 at 64r 2 at
240r
> merge %vreg26:2 at 240r into %vreg16:0 at 32r --> @32r
> pruned %vreg16 at 48r: [32r,48r:0)  0 at 32r
> pruned %vreg16 at 64r: [32r,48r:0)  0 at 32r
> pruned all of %vreg26 at 240r: [48r,64r:0)[64r,240r:1)  0 at 48r 1 at 64r 2
at 240r
> erased:240r%vreg26:sel_z<def> = COPY %vreg16<kill>; 
> R600_Reg128:%vreg26 R600_TReg32:%vreg16
> restoring liveness to 4 points: [32r,48r:0)[48r,64r:1)[64r,240r:2)  0 at
32r 1 at 48r
> 2 at 64r
> updated: 32B%vreg26:sel_z<def,read-undef> = COPY %T1_Z; 
> R600_Reg128:%vreg26
> Joined. Result = %vreg26[32r,48r:0)[48r,64r:1)[64r,336r:2)  0 at 32r 1 at
48r 2 at 64r
> 256B%vreg27<def> = COPY %vreg24; R600_Reg128:%vreg27,%vreg24
> Considering merging to R600_Reg128 with %vreg24 in %vreg27
> RHS = %vreg24 [128r,192r:0)[192r,256r:1)  0 at 128r 1 at 192r
> LHS = %vreg27 [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r
> merge %vreg27:1 at 256r into %vreg24:1 at 192r --> @192r
> erased:256r%vreg27<def> = COPY %vreg24; R600_Reg128:%vreg27,%vreg24
> updated: 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; 
> R600_Reg128:%vreg27
> updated: 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
> Joined. Result = %vreg27[128r,192r:0)[192r,272r:1)[272r,304r:2)  0 at 128r
1 at 192r
> 2 at 272r
> 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
> Not coalescable.
> 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> Considering merging %vreg28 with %C1_W
> RHS = %vreg28 [288r,320r:0)  0 at 288r
> updated: 320B%vreg3:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg3
> Joined. Result = %C1_W
> 304B%vreg3<def> = COPY %vreg27; R600_Reg128:%vreg3,%vreg27
> Considering merging to R600_Reg128 with %vreg27 in %vreg3
> RHS = %vreg3 [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r
> LHS = %vreg27 [128r,192r:0)[192r,272r:1)[272r,304r:2)  0 at 128r 1 at 192r
2 at 272r
> merge %vreg3:1 at 304r into %vreg27:2 at 272r --> @272r
> erased:304r%vreg3<def> = COPY %vreg27; R600_Reg128:%vreg3,%vreg27
> updated: 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
> updated: 416B%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
> Joined. Result =
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,416r:3)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r
> 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
> Not coalescable.
> 336B%vreg1<def> = COPY %vreg26; R600_Reg128:%vreg1,%vreg26
> Considering merging to R600_Reg128 with %vreg26 in %vreg1
> RHS = %vreg26 [32r,48r:0)[48r,64r:1)[64r,336r:2)  0 at 32r 1 at 48r 2 at
64r
> LHS = %vreg1 [336r,352r:1)[352r,832r:0)[880B,1168B:0)  0 at 352r 1 at 336r
> merge %vreg1:1 at 336r into %vreg26:2 at 64r --> @64r
> erased:336r%vreg1<def> = COPY %vreg26; R600_Reg128:%vreg1,%vreg26
> updated: 32B%vreg1:sel_z<def,read-undef> = COPY %T1_Z;
R600_Reg128:%vreg1
> updated: 64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
> updated: 48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[32r,48r:0)[48r,64r:1)[64r,352r:2)[352r,832r:3)[880B,1168B:3)  0 at
32r 1 at 48r
> 2 at 64r 3 at 352r
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 
> R600_TReg32:%vreg17
> Considering merging to R600_Reg128 with %vreg17 in %vreg1:sel_w
> RHS = %vreg17 [16r,352r:0)  0 at 16r
> LHS = %vreg1 [32r,48r:0)[48r,64r:1)[64r,352r:2)[352r,832r:3)[880B,1168B:3) 
>  0 at 32r 1 at 48r 2 at 64r 3 at 352r
> merge %vreg1:3 at 352r into %vreg17:0 at 16r --> @16r
> pruned %vreg17 at 32r: [16r,32r:0)  0 at 16r
> pruned %vreg17 at 48r: [16r,32r:0)  0 at 16r
> pruned %vreg17 at 64r: [16r,32r:0)  0 at 16r
> pruned all of %vreg1 at 352r: [32r,48r:0)[48r,64r:1)[64r,352r:2)  0 at 32r
1 at 48r
> 2 at 64r 3 at 352r
> erased:352r%vreg1:sel_w<def> = COPY %vreg17<kill>; 
> R600_Reg128:%vreg1 R600_TReg32:%vreg17
> restoring liveness to 8 points:
[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,352r:3)
>  0 at 16r 1 at 32r 2 at 48r 3 at 64r
> updated: 16B%vreg1:sel_w<def,read-undef> = COPY %T1_W;
R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r
1 at 32r
> 2 at 48r 3 at 64r
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> Considering merging %vreg0 with %C0_X
> RHS = %vreg0 [384r,592B:0)[880B,1168B:0)  0 at 384r
> updated: 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0,
0,
> %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
> Joined. Result = %C0_X
> 400B%vreg47<def> = COPY %C1_Y; R600_Reg32:%vreg47
> Considering merging %vreg47 with %C1_Y
> Cannot join defs into reserved register.
> 416B%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
> Considering merging to R600_Reg128 with %vreg27 in %vreg32
> RHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1168B:0)  0 at 448B-phi 1 at
416r
> LHS = %vreg27 [128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,416r:3)  0 at
128r
> 1 at 192r 2 at 272r 3 at 320r
> merge %vreg32:1 at 416r into %vreg27:3 at 320r --> @320r
> erased:416r%vreg32<def> = COPY %vreg27; R600_Reg128:%vreg32,%vreg27
> updated: 608B%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg27
> updated: 640B%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg27
> updated: 672B%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg27
> updated: 704B%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42 
> R600_Reg128:%vreg27
> updated: 976B%vreg10<def> = COPY %vreg27; R600_Reg128:%vreg10,%vreg27
> updated: 1040B%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w; 
> R600_Reg128:%vreg10,%vreg27
> updated: 1104B%vreg47<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg47 
> R600_Reg128:%vreg27
> Joined. Result = 
>
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> 432B%vreg49<def> = COPY %vreg13<kill>;
R600_Reg32:%vreg49,%vreg13
> Considering merging to R600_Reg32 with %vreg13 in %vreg49
> RHS = %vreg13 [368r,432r:0)  0 at 368r
> LHS = %vreg49 [432r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at
432r
> 1 at 448B-phi 2 at 1088r
> merge %vreg49:0 at 432r into %vreg13:0 at 368r --> @368r
> erased:432r%vreg49<def> = COPY %vreg13<kill>; 
> R600_Reg32:%vreg49,%vreg13
> updated: 368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0,
1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
> Joined. Result =
%vreg49[368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)
>  0 at 368r 1 at 448B-phi 2 at 1088r
> :
> 608B%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg27
> Considering merging to R600_Reg128 with %vreg39 in %vreg27:sel_x
> RHS = %vreg39 [608r,624r:0)  0 at 608r
> LHS = %vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> merge %vreg39:0 at 608r into %vreg27:4 at 448B --> @448B
> erased:608r%vreg39<def> = COPY %vreg27:sel_x; R600_Reg32:%vreg39 
> R600_Reg128:%vreg27
> updated: 624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
> Joined. Result = 
>
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> 624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
> Considering merging %vreg27 with %T2_XYZW
> Can only merge into reserved registers.
> 640B%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg27
> Considering merging to R600_Reg128 with %vreg40 in %vreg27:sel_y
> RHS = %vreg40 [640r,656r:0)  0 at 640r
> LHS = %vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> merge %vreg40:0 at 640r into %vreg27:4 at 448B --> @448B
> erased:640r%vreg40<def> = COPY %vreg27:sel_y; R600_Reg32:%vreg40 
> R600_Reg128:%vreg27
> updated: 656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
> Joined. Result = 
>
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> 656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
> Considering merging %vreg27 with %T2_XYZW
> Can only merge into reserved registers.
> 672B%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg27
> Considering merging to R600_Reg128 with %vreg41 in %vreg27:sel_z
> RHS = %vreg41 [672r,688r:0)  0 at 672r
> LHS = %vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> merge %vreg41:0 at 672r into %vreg27:4 at 448B --> @448B
> erased:672r%vreg41<def> = COPY %vreg27:sel_z; R600_Reg32:%vreg41 
> R600_Reg128:%vreg27
> updated: 688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
> Joined. Result = 
>
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> 688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
> Considering merging %vreg27 with %T2_XYZW
> Can only merge into reserved registers.
> 704B%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42 
> R600_Reg128:%vreg27
> Considering merging to R600_Reg128 with %vreg42 in %vreg27:sel_w
> RHS = %vreg42 [704r,720r:0)  0 at 704r
> LHS = %vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,704r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> merge %vreg42:0 at 704r into %vreg27:4 at 448B --> @448B
> erased:704r%vreg42<def> = COPY %vreg27:sel_w; R600_Reg32:%vreg42 
> R600_Reg128:%vreg27
> updated: 720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
> Joined. Result = 
>
%vreg27[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> 720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
> Considering merging %vreg27 with %T2_XYZW
> Can only merge into reserved registers.
> 736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 
> R600_Reg128:%vreg1
> Considering merging to R600_Reg128 with %vreg43 in %vreg1:sel_x
> RHS = %vreg43 [736r,752r:0)  0 at 736r
> LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0
at 16r
> 1 at 32r 2 at 48r 3 at 64r
> merge %vreg43:0 at 736r into %vreg1:3 at 64r --> @64r
> erased:736r%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 
> R600_Reg128:%vreg1
> updated: 752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r
1 at 32r
> 2 at 48r 3 at 64r
> 752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
> Considering merging %vreg1 with %T1_XYZW
> Can only merge into reserved registers.
> 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 
> R600_Reg128:%vreg1
> Considering merging to R600_Reg128 with %vreg44 in %vreg1:sel_y
> RHS = %vreg44 [768r,784r:0)  0 at 768r
> LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0
at 16r
> 1 at 32r 2 at 48r 3 at 64r
> merge %vreg44:0 at 768r into %vreg1:3 at 64r --> @64r
> erased:768r%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 
> R600_Reg128:%vreg1
> updated: 784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r
1 at 32r
> 2 at 48r 3 at 64r
> 784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
> Considering merging %vreg1 with %T1_XYZW
> Can only merge into reserved registers.
> 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 
> R600_Reg128:%vreg1
> Considering merging to R600_Reg128 with %vreg45 in %vreg1:sel_z
> RHS = %vreg45 [800r,816r:0)  0 at 800r
> LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0
at 16r
> 1 at 32r 2 at 48r 3 at 64r
> merge %vreg45:0 at 800r into %vreg1:3 at 64r --> @64r
> erased:800r%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 
> R600_Reg128:%vreg1
> updated: 816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0 at 16r
1 at 32r
> 2 at 48r 3 at 64r
> 816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
> Considering merging %vreg1 with %T1_XYZW
> Can only merge into reserved registers.
> 832B%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 
> R600_Reg128:%vreg1
> Considering merging to R600_Reg128 with %vreg46 in %vreg1:sel_w
> RHS = %vreg46 [832r,848r:0)  0 at 832r
> LHS = %vreg1 [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,832r:3)[880B,1168B:3)  0
at 16r
> 1 at 32r 2 at 48r 3 at 64r
> merge %vreg46:0 at 832r into %vreg1:3 at 64r --> @64r
> erased:832r%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 
> R600_Reg128:%vreg1
> updated: 848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
> Joined. Result = 
> %vreg1[16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at 16r
1 at 32r
> 2 at 48r 3 at 64r
> 848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
> Considering merging %vreg1 with %T1_XYZW
> Can only merge into reserved registers.
> 976B%vreg10<def> = COPY %vreg27; R600_Reg128:%vreg10,%vreg27
> Considering merging to R600_Reg128 with %vreg27 in %vreg10
> RHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at
992r 2 at 1040r
> LHS = %vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> merge %vreg10:0 at 976r into %vreg27:4 at 448B --> @448B
> interference at %vreg10:1 at 992r
> Interference!
> 992B%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 
> R600_Reg32:%vreg47
> Considering merging to R600_Reg128 with %vreg47 in %vreg10:sel_z
> RHS = %vreg47 [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at
400r
> 1 at 448B-phi 2 at 1104r
> LHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1040d:2)  0 at 976r 1 at
992r 2 at 1040r
> interference at %vreg10:0 at 976r
> Interference!
> 1040B%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w; 
> R600_Reg128:%vreg10,%vreg27
> Copy is dead.
> Deleting dead def 1040r%vreg10:sel_w<def,dead> = COPY %vreg27:sel_w; 
> R600_Reg128:%vreg10,%vreg27
> Shrink: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
>  live-in at 592B
>  live-in at 880B
> Shrunk: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> Shrink: [976r,992r:0)[992r,1040r:1)  0 at 976r 1 at 992r
> All defs dead: 992r%vreg10:sel_z<def,dead> = COPY %vreg47; 
> R600_Reg128:%vreg10 R600_Reg32:%vreg47
> Shrunk: [976r,992r:0)[992r,992d:1)  0 at 976r 1 at 992r
> Deleting dead def 992r%vreg10:sel_z<def,dead> = COPY %vreg47; 
> R600_Reg128:%vreg10 R600_Reg32:%vreg47
> Shrink: [400r,448B:0)[448B,592B:1)[880B,992r:1)[1104r,1168B:2)  0 at 400r 
> 1 at 448B-phi 2 at 1104r
> All defs dead: 400r%vreg47<def,dead> = COPY %C1_Y; R600_Reg32:%vreg47
> Dead PHI at invalid may separate interval
> All defs dead: 1104r%vreg47<def,dead> = COPY %vreg27:sel_z; 
> R600_Reg32:%vreg47 R600_Reg128:%vreg27
> Shrunk: [400r,400d:0)[1104r,1104d:2)  0 at 400r 1 at x 2 at 1104r
> 2 components: [400r,400d:0)[1104r,1104d:1)  0 at 400r 1 at 1104r
> [400r,400d:0)  0 at 400r
> [1104r,1104d:0)  0 at 1104r
> Deleting dead def 1104r%vreg50<def,dead> = COPY %vreg27:sel_z; 
> R600_Reg32:%vreg50 R600_Reg128:%vreg27
> Deleting dead def 400r%vreg47<def,dead> = COPY %C1_Y;
R600_Reg32:%vreg47
> Shrink: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
>  live-in at 592B
>  live-in at 880B
> Shrunk: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> Shrink: [976r,992r:0)  0 at 976r
> All defs dead: 976r%vreg10<def,dead> = COPY %vreg27; 
> R600_Reg128:%vreg10,%vreg27
> Shrunk: [976r,976d:0)  0 at 976r
> Deleting dead def 976r%vreg10<def,dead> = COPY %vreg27; 
> R600_Reg128:%vreg10,%vreg27
> Shrink: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
>  live-in at 592B
>  live-in at 880B
> Shrunk: 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> Trying to inflate 0 regs.
> ********** INTERVALS **********
> C0_X = EMPTY
> C1_W = EMPTY
> C1_X = EMPTY
> C1_Y = EMPTY
> C1_Z = EMPTY
> T1_W = [0B,16r:0)[848r,864r:1)  0 at 0B-phi 1 at 848r
> T1_X = [0B,64r:0)[752r,864r:1)  0 at 0B-phi 1 at 752r
> T1_Y = [0B,48r:0)[784r,864r:1)  0 at 0B-phi 1 at 784r
> T1_Z = [0B,32r:0)[816r,864r:1)  0 at 0B-phi 1 at 816r
> %vreg1 = [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at
16r
> 1 at 32r 2 at 48r 3 at 64r
> %vreg27 = 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> %vreg30 = [512r,544r:0)  0 at 512r
> %vreg38 = [1072r,1088r:0)  0 at 1072r
> %vreg49 = [368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at
368r
> 1 at 448B-phi 2 at 1088r
> ********** MACHINEINSTRS **********
> # Machine code for function main: Post SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16,
%T1_W
> in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
> 
> 0BBB#0: derived from LLVM BB %0
>    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> 16B%vreg1:sel_w<def,read-undef> = COPY %T1_W; R600_Reg128:%vreg1
> 32B%vreg1:sel_z<def> = COPY %T1_Z; R600_Reg128:%vreg1
> 48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
> 64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
> 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27
> 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
> 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
> 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
> 368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
>    Successors according to CFG: BB#1
> 
> 448BBB#1: derived from LLVM BB %25
>    Predecessors according to CFG: BB#0 BB#3
> 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0,
%vreg49, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
>    Successors according to CFG: BB#2(4) BB#3(124)
> 
> 592BBB#2: derived from LLVM BB %31
>    Predecessors according to CFG: BB#1
> 624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
> 656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
> 688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
> 720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
> 752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
> 784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
> 816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
> 848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
> 864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>,
%T1_Y<imp-use>,
> %T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>,
> %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
> 
> 880BBB#3: derived from LLVM BB %41
>    Predecessors according to CFG: BB#1
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> 1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, 
> %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg49,%vreg38
> 1152BJUMP <BB#1>, pred:%noreg
>    Successors according to CFG: BB#1
> 
> # End machine code for function main.
> 
> ********** DEBUG VARIABLES **********
> ********** GREEDY REGISTER ALLOCATION **********
> ********** Function: main
> 
> selectOrSplit R600_Reg128:%vreg1 
> [16r,32r:0)[32r,48r:1)[48r,64r:2)[64r,848r:3)[880B,1168B:3)  0 at 16r 1 at
32r 2 at 48r
> 3 at 64r
> AllocationOrder(R600_Reg128) = [ %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW
%T5_XYZW
> %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW %T13_XYZW
> %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW
%T21_XYZW
> %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW
%T29_XYZW
> %T30_XYZW %T31_XYZW %T32_XYZW %T33_XYZW %T34_XYZW %T35_XYZW %T36_XYZW
%T37_XYZW
> %T38_XYZW %T39_XYZW %T40_XYZW %T41_XYZW %T42_XYZW %T43_XYZW %T44_XYZW
%T45_XYZW
> %T46_XYZW %T47_XYZW %T48_XYZW %T49_XYZW %T50_XYZW %T51_XYZW %T52_XYZW
%T53_XYZW
> %T54_XYZW %T55_XYZW %T56_XYZW %T57_XYZW %T58_XYZW %T59_XYZW %T60_XYZW
%T61_XYZW
> %T62_XYZW %T63_XYZW %T64_XYZW %T65_XYZW %T66_XYZW %T67_XYZW %T68_XYZW
%T69_XYZW
> %T70_XYZW %T71_XYZW %T72_XYZW %T73_XYZW %T74_XYZW %T75_XYZW %T76_XYZW
%T77_XYZW
> %T78_XYZW %T79_XYZW %T80_XYZW %T81_XYZW %T82_XYZW %T83_XYZW %T84_XYZW
%T85_XYZW
> %T86_XYZW %T87_XYZW %T88_XYZW %T89_XYZW %T90_XYZW %T91_XYZW %T92_XYZW
%T93_XYZW
> %T94_XYZW
> %T95_XYZW %T96_XYZW %T97_XYZW %T98_XYZW %T99_XYZW %T100_XYZW %T101_XYZW 
> %T102_XYZW %T103_XYZW %T104_XYZW %T105_XYZW %T106_XYZW %T107_XYZW
%T108_XYZW
> %T109_XYZW %T110_XYZW %T111_XYZW %T112_XYZW %T113_XYZW %T114_XYZW
%T115_XYZW
> %T116_XYZW %T117_XYZW %T118_XYZW %T119_XYZW %T120_XYZW %T121_XYZW
%T122_XYZW
> %T123_XYZW %T124_XYZW %T125_XYZW %T126_XYZW %T127_XYZW ]
> assigning %vreg1 to %T1_XYZW: T1_W T1_X T1_Y T1_Z
> 
> selectOrSplit R600_Reg128:%vreg27 
>
[128r,192r:0)[192r,272r:1)[272r,320r:2)[320r,448B:3)[448B,720r:4)[880B,1168B:4)
>  0 at 128r 1 at 192r 2 at 272r 3 at 320r 4 at 448B-phi
> assigning %vreg27 to %T2_XYZW: T2_W T2_X T2_Y T2_Z
> 
> selectOrSplit R600_Reg32:%vreg49 
> [368r,448B:0)[448B,592B:1)[880B,1088r:1)[1088r,1168B:2)  0 at 368r 1 at
448B-phi
> 2 at 1088r
> AllocationOrder(R600_Reg32) = [ %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z
%T2_W
> %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W
%T6_X
> %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X
%T9_Y
> %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %T11_Z %T11_W %T12_X 
> %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X %T14_Y %T14_Z
%T14_W
> %T15_X %T15_Y %T15_Z %T15_W %T16_X %T16_Y %T16_Z %T16_W %T17_X %T17_Y
%T17_Z
> %T17_W %T18_X %T18_Y %T18_Z %T18_W %T19_X %T19_Y %T19_Z %T19_W %T20_X
%T20_Y
> %T20_Z %T20_W %T21_X %T21_Y %T21_Z %T21_W %T22_X %T22_Y %T22_Z %T22_W
%T23_X
> %T23_Y %T23_Z %T23_W %T24_X %T24_Y %T24_Z %T24_W %T25_X %T25_Y %T25_Z
%T25_W
> %T26_X %T26_Y %T26_Z %T26_W %T27_X %T27_Y %T27_Z %T27_W %T28_X %T28_Y
%T28_Z
> %T28_W %T29_X %T29_Y %T29_Z %T29_W %T30_X %T30_Y %T30_Z %T30_W %T31_X
%T31_Y
> %T31_Z %T31_W %T32_X %T32_Y %T32_Z %T32_W %T33_X %T33_Y %T33_Z %T33_W
%T34_X
> %T34_Y %T34_Z %T34_W %T35_X %T35_Y %T35_Z
> %T35_W %T36_X %T36_Y %T36_Z %T36_W %T37_X %T37_Y %T37_Z %T37_W %T38_X
%T38_Y
> %T38_Z %T38_W %T39_X %T39_Y %T39_Z %T39_W %T40_X %T40_Y %T40_Z %T40_W
%T41_X
> %T41_Y %T41_Z %T41_W %T42_X %T42_Y %T42_Z %T42_W %T43_X %T43_Y %T43_Z
%T43_W
> %T44_X %T44_Y %T44_Z %T44_W %T45_X %T45_Y %T45_Z %T45_W %T46_X %T46_Y
%T46_Z
> %T46_W %T47_X %T47_Y %T47_Z %T47_W %T48_X %T48_Y %T48_Z %T48_W %T49_X
%T49_Y
> %T49_Z %T49_W %T50_X %T50_Y %T50_Z %T50_W %T51_X %T51_Y %T51_Z %T51_W
%T52_X
> %T52_Y %T52_Z %T52_W %T53_X %T53_Y %T53_Z %T53_W %T54_X %T54_Y %T54_Z
%T54_W
> %T55_X %T55_Y %T55_Z %T55_W %T56_X %T56_Y %T56_Z %T56_W %T57_X %T57_Y
%T57_Z
> %T57_W %T58_X %T58_Y %T58_Z %T58_W %T59_X %T59_Y %T59_Z %T59_W %T60_X
%T60_Y
> %T60_Z %T60_W %T61_X %T61_Y %T61_Z %T61_W %T62_X %T62_Y %T62_Z %T62_W
%T63_X
> %T63_Y %T63_Z %T63_W %T64_X %T64_Y %T64_Z %T64_W %T65_X %T65_Y %T65_Z
%T65_W
> %T66_X %T66_Y %T66_Z %T66_W %T67_X %T67_Y %T67_Z %T67_W %T68_X %T68_Y
%T68_Z
> %T68_W %T69_X %T69_Y %T69_Z %T69_W %T70_X
> %T70_Y %T70_Z %T70_W %T71_X %T71_Y %T71_Z %T71_W %T72_X %T72_Y %T72_Z
%T72_W
> %T73_X %T73_Y %T73_Z %T73_W %T74_X %T74_Y %T74_Z %T74_W %T75_X %T75_Y
%T75_Z
> %T75_W %T76_X %T76_Y %T76_Z %T76_W %T77_X %T77_Y %T77_Z %T77_W %T78_X
%T78_Y
> %T78_Z %T78_W %T79_X %T79_Y %T79_Z %T79_W %T80_X %T80_Y %T80_Z %T80_W
%T81_X
> %T81_Y %T81_Z %T81_W %T82_X %T82_Y %T82_Z %T82_W %T83_X %T83_Y %T83_Z
%T83_W
> %T84_X %T84_Y %T84_Z %T84_W %T85_X %T85_Y %T85_Z %T85_W %T86_X %T86_Y
%T86_Z
> %T86_W %T87_X %T87_Y %T87_Z %T87_W %T88_X %T88_Y %T88_Z %T88_W %T89_X
%T89_Y
> %T89_Z %T89_W %T90_X %T90_Y %T90_Z %T90_W %T91_X %T91_Y %T91_Z %T91_W
%T92_X
> %T92_Y %T92_Z %T92_W %T93_X %T93_Y %T93_Z %T93_W %T94_X %T94_Y %T94_Z
%T94_W
> %T95_X %T95_Y %T95_Z %T95_W %T96_X %T96_Y %T96_Z %T96_W %T97_X %T97_Y
%T97_Z
> %T97_W %T98_X %T98_Y %T98_Z %T98_W %T99_X %T99_Y %T99_Z %T99_W %T100_X
%T100_Y
> %T100_Z %T100_W %T101_X %T101_Y %T101_Z %T101_W %T102_X %T102_Y %T102_Z
%T102_W
> %T103_X %T103_Y %T103_Z %T103_W
> %T104_X %T104_Y %T104_Z %T104_W %T105_X %T105_Y %T105_Z %T105_W %T106_X
%T106_Y
> %T106_Z %T106_W %T107_X %T107_Y %T107_Z %T107_W %T108_X %T108_Y %T108_Z
%T108_W
> %T109_X %T109_Y %T109_Z %T109_W %T110_X %T110_Y %T110_Z %T110_W %T111_X
%T111_Y
> %T111_Z %T111_W %T112_X %T112_Y %T112_Z %T112_W %T113_X %T113_Y %T113_Z
%T113_W
> %T114_X %T114_Y %T114_Z %T114_W %T115_X %T115_Y %T115_Z %T115_W %T116_X
%T116_Y
> %T116_Z %T116_W %T117_X %T117_Y %T117_Z %T117_W %T118_X %T118_Y %T118_Z
%T118_W
> %T119_X %T119_Y %T119_Z %T119_W %T120_X %T120_Y %T120_Z %T120_W %T121_X
%T121_Y
> %T121_Z %T121_W %T122_X %T122_Y %T122_Z %T122_W %T123_X %T123_Y %T123_Z
%T123_W
> %T124_X %T124_Y %T124_Z %T124_W %T125_X %T125_Y %T125_Z %T125_W %T126_X
%T126_Y
> %T126_Z %T126_W %T127_X %T127_Y %T127_Z %T127_W %ArrayBase448 %ArrayBase449
> %ArrayBase450 %ArrayBase451 %ArrayBase452 %ArrayBase453 %ArrayBase454 
> %ArrayBase455 %ArrayBase456 %ArrayBase457 %ArrayBase458 %ArrayBase459 
> %ArrayBase460 %ArrayBase461
> %ArrayBase462 %ArrayBase463 %ArrayBase464 ]
> assigning %vreg49 to %T3_X: T3_X
> 
> selectOrSplit R600_Reg32:%vreg30 [512r,544r:0)  0 at 512r
> assigning %vreg30 to %T3_Y: T3_Y
> 
> selectOrSplit R600_Reg32:%vreg38 [1072r,1088r:0)  0 at 1072r
> assigning %vreg38 to %T3_Y: T3_Y
> ********** REWRITE VIRTUAL REGISTERS **********
> ********** Function: main
> ********** REGISTER MAP **********
> [%vreg1 -> %T1_XYZW] R600_Reg128
> [%vreg27 -> %T2_XYZW] R600_Reg128
> [%vreg30 -> %T3_Y] R600_Reg32
> [%vreg38 -> %T3_Y] R600_Reg32
> [%vreg49 -> %T3_X] R600_Reg32
> 
> 0BBB#0: derived from LLVM BB %0
>    Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> 16B%vreg1:sel_w<def,read-undef> = COPY %T1_W; R600_Reg128:%vreg1
> 32B%vreg1:sel_z<def> = COPY %T1_Z; R600_Reg128:%vreg1
> 48B%vreg1:sel_y<def> = COPY %T1_Y; R600_Reg128:%vreg1
> 64B%vreg1:sel_x<def> = COPY %T1_X; R600_Reg128:%vreg1
> 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27
> 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27
> 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27
> 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27
> 368B%vreg49<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg49
>    Successors according to CFG: BB#1
>>  %T1_W<def> = COPY %T1_W, %T1_XYZW<imp-def>
> Identity copy: %T1_W<def> = KILL %T1_W, %T1_XYZW<imp-def>
>>  %T1_Z<def> = COPY %T1_Z, %T1_XYZW<imp-use,kill>, 
> %T1_XYZW<imp-def>
> Identity copy: %T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>,
> %T1_XYZW<imp-def>
>>  %T1_Y<def> = COPY %T1_Y, %T1_XYZW<imp-use,kill>, 
> %T1_XYZW<imp-def>
> Identity copy: %T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>,
> %T1_XYZW<imp-def>
>>  %T1_X<def> = COPY %T1_X, %T1_XYZW<imp-use,kill>, 
> %T1_XYZW<imp-def>
> Identity copy: %T1_X<def> = KILL %T1_X, %T1_XYZW<imp-use,kill>,
> %T1_XYZW<imp-def>
>>  %T2_X<def> = COPY %C1_X, %T2_XYZW<imp-def>
>>  %T2_Y<def> = COPY %C1_Y, %T2_XYZW<imp-use,kill>, 
> %T2_XYZW<imp-def>
>>  %T2_Z<def> = COPY %C1_Z, %T2_XYZW<imp-use,kill>, 
> %T2_XYZW<imp-def>
>>  %T2_W<def> = COPY %C1_W, %T2_XYZW<imp-use,kill>, 
> %T2_XYZW<imp-def>
>>  %T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 0
> 448BBB#1: derived from LLVM BB %25
>    Live Ins: %T1_XYZW %T2_XYZW %T3_X
>    Predecessors according to CFG: BB#0 BB#3
> 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0,
%vreg49, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; 
> R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
>    Successors according to CFG: BB#2(4) BB#3(124)
>>  %T3_Y<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %T3_X,
0, 0,
> 0, 1, pred:%PRED_SEL_OFF, 0
>>  %PREDICATE_BIT<def> = PRED_X %T3_Y<kill>, 152, 16
>>  JUMP <BB#3>, pred:%PREDICATE_BIT
>>  JUMP <BB#2>, pred:%noreg
> 592BBB#2: derived from LLVM BB %31
>    Live Ins: %T1_XYZW %T2_XYZW
>    Predecessors according to CFG: BB#1
> 624B%T2_X<def> = COPY %vreg27:sel_x; R600_Reg128:%vreg27
> 656B%T2_Y<def> = COPY %vreg27:sel_y; R600_Reg128:%vreg27
> 688B%T2_Z<def> = COPY %vreg27:sel_z; R600_Reg128:%vreg27
> 720B%T2_W<def> = COPY %vreg27:sel_w; R600_Reg128:%vreg27
> 752B%T1_X<def> = COPY %vreg1:sel_x; R600_Reg128:%vreg1
> 784B%T1_Y<def> = COPY %vreg1:sel_y; R600_Reg128:%vreg1
> 816B%T1_Z<def> = COPY %vreg1:sel_z; R600_Reg128:%vreg1
> 848B%T1_W<def> = COPY %vreg1:sel_w; R600_Reg128:%vreg1
> 864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>,
%T1_Y<imp-use>,
> %T1_X<imp-use>, %T2_W<imp-use>, %T2_Z<imp-use>, 
> %T2_Y<imp-use>, %T2_X<imp-use>
>>  %T2_X<def> = COPY %T2_X
> Deleting identity copy.
>>  %T2_Y<def> = COPY %T2_Y
> Deleting identity copy.
>>  %T2_Z<def> = COPY %T2_Z
> Deleting identity copy.
>>  %T2_W<def> = COPY %T2_W
> Deleting identity copy.
>>  %T1_X<def> = COPY %T1_X
> Deleting identity copy.
>>  %T1_Y<def> = COPY %T1_Y
> Deleting identity copy.
>>  %T1_Z<def> = COPY %T1_Z
> Deleting identity copy.
>>  %T1_W<def> = COPY %T1_W
> Deleting identity copy.
>>  RETURN %T1_W<imp-use>, %T1_Z<imp-use>,
%T1_Y<imp-use>,
> %T1_X<imp-use>, %T2_W<imp-use>, %T2_Z<imp-use>, 
> %T2_Y<imp-use>, %T2_X<imp-use>
> 880BBB#3: derived from LLVM BB %41
>    Live Ins: %T1_XYZW %T2_XYZW %T3_X
>    Predecessors according to CFG: BB#1
> 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
> 1088B%vreg49<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49<kill>, 0,
0,
> 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; 
> R600_Reg32:%vreg49,%vreg38
> 1152BJUMP <BB#1>, pred:%noreg
>    Successors according to CFG: BB#1
>>  %T3_Y<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, 
> pred:%PRED_SEL_OFF, 1
>>  %T3_X<def> = ADD_INT 0, 0, 1, 0, 0, 0, %T3_X<kill>, 0, 0,
0,
> %T3_Y<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0
>>  JUMP <BB#1>, pred:%noreg
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu        http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

Ivan Llopard

2012-Oct-25 19:54 UTC

head link

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

Hi Vincent,

On 25/10/2012 18:14, Vincent Lejeune wrote:> When examining the debug output of regalloc, it seems that joining 32bits
reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and vreg48 are joined. It's right.
>
> But joining the following copy
>
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;
R600_Reg128:%vreg32,%vreg48
>
> updates it to
> 928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34
R600_Reg128:%vreg32
>
> which is wrong. vreg32:sel_y is undef.
Well, that seems correct to me. Following the code and debug output, the 
joining is going from vreg6->vreg48->vreg32. vreg6 is defined at BB0, so 
it will be vreg32 and its sel_y subreg also.
Try to run the verifier with -verify-coalescing.
If you have implemented the hooks for the coalescer in your 
TargetRegisterInfo you can also try to disable them to verify the 
implementation. Hope this helps to spot the problem.

Ivan
>
> Regards,
> Vincent
>

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llvm dev - Oct 2012 - [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.

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