search for: sel_y

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and vreg48 are joined. It's right. > > But joining the following copy > > 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48...

...PY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 %vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 %vreg26<def&...

...t;; R600_Reg128:%vreg19 R600_TReg32:%vreg14 > %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 > %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 > %vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 > %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 > %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 > %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25...

When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. If I look at the : %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 instructions ; it gets joined to : 928B%vreg34<def> = COPY %vreg48:sel_y;  when vreg6 and vreg48 are joined. It's right. But joining the following copy  912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; R600_Reg128:%vreg32,%vreg48 up...

...eg2 register: %vreg2 +[112r,400r:0) 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 register: %vreg21 +[128r,176r:0) 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 register: %vreg23 +[144r,224r:0) 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 register: %vreg24 +[176r,256r:0) 1...

...gt;, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg // LOOP BODY 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35 992B%v...

...576BJUMP <BB#2>, pred:%noreg > > // LOOP BODY > 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 > 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 > 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 > 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 > 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36...

...%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10 %vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6 RESERVE_REG 1 RESERVE_REG 2 %vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8 %vreg13<def> = IMPLICIT_DEF; R600_Reg32:%vreg13 %vreg12<def,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13 RESERVE_REG 3 %vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15 %vreg...

...------------------===// > +// > +// Tablegen register definitions common to all hw codegen targets. > +// > +//===----------------------------------------------------------------------===// > + > +let Namespace = "AMDGPU" in { > + def sel_x : SubRegIndex; > + def sel_y : SubRegIndex; > + def sel_z : SubRegIndex; > + def sel_w : SubRegIndex; > +} > + > +include "R600RegisterInfo.td" > +include "SIRegisterInfo.td" > > Added: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h > URL: http://llvm.org/viewvc/llvm-project/ll...