Displaying 9 results from an estimated 9 matches for "sel_w".
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sel_x
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25
%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0,...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...= COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
> %vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25
> %vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> %vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
> %vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
> %vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
> %vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
> %vreg13<def> = MOV 1, 0, 0, 0, %ALU_L...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...7 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0) 0 at 272r 1 at 256r
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
register: %vreg28 +[288r,320r:0)
304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
register: %vreg3 +[304r,416r:0)
320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
register: %vreg3 replace range with [304r,320r:1) RESULT: [304r,320r:1)[320r,416r:0) 0 at 320r 1 at 304r
336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
register: %vreg1 +[336r,448B:0) +[448B,...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...:1) RESULT:
> [256r,272r:1)[272r,304r:0) 0 at 272r 1 at 256r
> 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> register: %vreg28 +[288r,320r:0)
> 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
> register: %vreg3 +[304r,416r:0)
> 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3
> R600_Reg32:%vreg28
> register: %vreg3 replace range with [304r,320r:1) RESULT:
> [304r,320r:1)[320r,416r:0) 0 at 320r 1 at 304r
> 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
> register: %v...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...eg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34
976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg1...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ef> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34
> 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
> 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5
> 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
> 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
> 1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37
> 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...IMPLICIT_DEF; R600_Reg32:%vreg13
%vreg12<def,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13
RESERVE_REG 3
%vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15
%vreg14<def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15
%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3
%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14
%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2
%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg1...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...tions common to all hw codegen targets.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +let Namespace = "AMDGPU" in {
> + def sel_x : SubRegIndex;
> + def sel_y : SubRegIndex;
> + def sel_z : SubRegIndex;
> + def sel_w : SubRegIndex;
> +}
> +
> +include "R600RegisterInfo.td"
> +include "SIRegisterInfo.td"
>
> Added: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=160270&view=a...