Displaying 11 results from an estimated 11 matches for "sel_z".
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sel_x
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...g32:%vreg15
%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25
%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
%...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...place range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0) 0 at 240r 1 at 224r
256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
register: %vreg27 +[256r,304r:0)
2...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...RESULT:
> [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +[208r,272r:0)
> 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
> register: %vreg26 +[224r,336r:0)
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> register: %vreg26 replace range with [224r,240r:1) RESULT:
> [224r,240r:1)[240r,336r:0) 0 at 240r 1 at 224r
> 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
> registe...
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...lt;def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
> %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
> %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> %vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
> %vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
> %vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
> %vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25
> %vreg28<def> = COPY %C1_W; R600_...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...Reg128:%vreg6
> 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
> 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34
> 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
> 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5
> 1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
> 1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
> 1040B%vreg10:sel_w<def> = COPY %vreg37&...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
..._Reg32:%vreg34 R600_Reg128:%vreg6
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34
976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R6...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
Hi,
below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
It worked with llvm 3.1, I don't know if there was a requirement intro...
2012 Oct 20
0
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote:
> below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
> The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
>
> I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
> It worked with llvm 3.1, I don't know if there was a re...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...;
>
>On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote:
>
>below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
>>The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
>>
>>I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
>>It worked with llvm 3.1, I don't know if there...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...> +// Tablegen register definitions common to all hw codegen targets.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +let Namespace = "AMDGPU" in {
> + def sel_x : SubRegIndex;
> + def sel_y : SubRegIndex;
> + def sel_z : SubRegIndex;
> + def sel_w : SubRegIndex;
> +}
> +
> +include "R600RegisterInfo.td"
> +include "SIRegisterInfo.td"
>
> Added: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU...