Displaying 8 results from an estimated 8 matches for "r600_treg32".
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r600_reg32
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...s ***:
# Machine code for function main: SSA
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_W %T1_Z %T1_Y %T1_X
%vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3
%vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2
%vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1
%vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0
RESERVE_REG 0
%vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3
%vreg5<def> = MOV_IMM_F32 0.000000e+00; R600...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...achine code for function main: Post SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vre...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...Post SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> BB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> %vreg19:sel_x<def,read-undef> = COPY %vreg14<k...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...:
# Machine code for function main: SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
%vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
%vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20
%vreg19<def,tie...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...main: SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> BB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
> %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18
> %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t seems the PhiElim is working correctly, the output of --debug-only=regalloc shows that %vreg48 is a phi-join register, and intervals looks correct to me :
********** COMPUTING LIVE INTERVALS **********
********** Function: main
BB#0:# derived from
16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
register: %vreg17 +[16r,352r:0)
32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...correctly, the output of --debug-only=regalloc
> shows that %vreg48 is a phi-join register, and intervals looks correct to me :
>
> ********** COMPUTING LIVE INTERVALS **********
> ********** Function: main
> BB#0:# derived from
> 16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
> register: %vreg17 +[16r,352r:0)
> 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY...