Displaying 17 results from an estimated 17 matches for "vreg32".
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rreg32
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and vreg48 are joined. It's right.
>
> But joining the following copy
>
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; R600_Reg128:%vreg32,%vreg48
>
> updates it to
> 928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg32
>
> which is wrong. vreg32:sel_y is undef.
Well, that seems correct to me. Following the code and deb...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives...
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Vincent,
File a bug report so you can get a fix for it.
Ivan
On 25/10/2012 23:01, Vincent Lejeune wrote:
> Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
> I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
> vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vre...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
BB#3:# derived from
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
register: %vreg31 +[896r,912r:0)
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
register: %vreg32 +[912r,944r:0)
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
register: %vreg34 +[928r,960r:0)
944B%vreg35<def> = COPY %vreg32<kill>; R600_...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...eg also joins 128 parent reg.
If I look at the :
%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
instructions ; it gets joined to :
928B%vreg34<def> = COPY %vreg48:sel_y;
when vreg6 and vreg48 are joined. It's right.
But joining the following copy
912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x; R600_Reg128:%vreg32,%vreg48
updates it to
928B%vreg34<def> = COPY %vreg32:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg32
which is wrong. vreg32:sel_y is undef.
Regards,
Vincent
----- Mail original -----
> De : Vincent Lejeune <vljn...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...gt; 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%noreg
>
> // LOOP BODY
> 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
> 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
> 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
> 960B%vreg35:sel_y<def>...
2012 Jul 06
0
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...e if A3 is a subreg define while A3 is not a subreg
use.
For instance, consider this code (part of a single block loop).
MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30,
2, // Post Inc. Load. Vreg7 is a 64bit reg.
MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill>
// This is the A3 = B0 above.
MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill>
// Use the lo subreg that was setup in MI1:
....
....
MI4:: %vreg32<def> = COPY %vreg7; //Not trivial
because 7 is not kil...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
// LOOP BODY
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
960B%vreg35:sel_y<def> = COPY %vreg34...
2012 Jul 05
3
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob,
Thanks for your reply.
>
> The <undef> flag goes on NewMI_1 because the virtual register B isn't live
> before that instruction.
>
> But you probably shouldn't be doing this yourself. Your NewMI code isn't
in
> SSA form because B has multiple definitions. Just use a REG_SEQUENCE
> instruction, and let the register allocator do the transformation
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...1: v8i64 = VLOAD_D TargetConstant:i64<0>
t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
t8: ch = TokenFactor t3, t6
t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
[...]
Spilling live registers at end of block.
Spilling %vreg31 in %R0 to stack slot #5
Spilling %vreg32 in %Wd0 to stack slot #6
BB#3: derived from LLVM BB %vector.body.preheader
Predecessors according to CFG: BB#2
%Wd0<def> = VLOAD_D 0
%R0<def> = MOV_ri 0
STD %R0<kill>, <fi#5>, 0
STD %Wd0<kill>, <fi#6>, 0
JMP <B...
2012 Jul 06
2
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...le A3 is not a subreg
> use.
> For instance, consider this code (part of a single block loop).
>
> MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30,
> 2, // Post Inc. Load. Vreg7 is a 64bit reg.
> MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill>
> // This is the A3 = B0 above.
> MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill>
> // Use the lo subreg that was setup in MI1:
> ....
> ....
> MI4:: %vreg32<def> = COPY %vreg7; //No...
2014 Jul 09
6
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...(align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function
yalong at multicorewareinc.com
From: Kevin QinDate:...
2014 Jul 09
2
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function�
� � Anyone can help me?? Thank you agai...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...;
> t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11
> t8: ch = TokenFactor t3, t6
> t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8
>
> [...]
>
> Spilling live registers at end of block.
> Spilling %vreg31 in %R0 to stack slot #5
> Spilling %vreg32 in %Wd0 to stack slot #6
> BB#3: derived from LLVM BB %vector.body.preheader
> Predecessors according to CFG: BB#2
> %Wd0<def> = VLOAD_D 0
> %R0<def> = MOV_ri 0
> STD %R0<kill>, <fi#5>, 0
> STD %Wd0<kill>, <...
2016 Feb 03
2
[buildSchedGraph] memory dependencies
...wOffset == OffsetA) ? WidthA : WidthB;
+ if (LowOffset + LowWidth <= HighOffset)
+ return false;
+ }
+
if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb,
MFI, DL))
return true;
2) The TBAA tags should separate the loads from the stores. In the MF I see
...
%vreg32<def> = L %vreg0, 56, %noreg;
mem:LD4[%src1(align=64)+56](align=8)(tbaa=!1) GR32Bit:%vreg32
ADDR64Bit:%vreg0
...
ST %vreg33, %vreg1, 60, %noreg;
mem:ST4[%dest(align=64)+60](align=4)(tbaa=!4) GR32Bit:%vreg33
ADDR64Bit:%vreg1
...
Since the tbba tags are part of the MachineMemOperands, it is...
2014 Jul 10
2
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...gn=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
0x9f54ba8: i32 = FrameIndex<0> [ID=24]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]
In function: testVCVTT32TO16Function
yalong at multicorewareinc.com...
2014 Jul 09
4
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...t; 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40,
>> 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
>> 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
>> 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
>> 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
>> 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
>> 0x9f54b20: i32 = undef [ORD=1797] [ID=6]
>> 0x9f54ba8: i32 = FrameIndex<0> [ID=24]
>> 0x9f54b20: i32 = undef [ORD=1797] [ID=6]
>> In function: testVCVTT32TO16Function
>>
>>...