llvm dev - Jul 2012 - [LLVMdev] Issue with Machine Verifier and earlyclobber

Hello,

I'm getting a machine verifier error after introducing the earlyclobber
constraint to some instructions where the src and dest regs can't be the
same. The offending instruction pattern is this one:

let canFoldAsLoad = 1,
isReMaterializable = 1,
Constraints = "@earlyclobber $dst" in
def LDDWRdPtrQ : Inst<(outs DREGS:$dst),
                        (ins memri:$src),
                        "lddw\t$dst, $src",
                        [(set DREGS:$dst, (load addr:$src))]>;

This is just a load with displacement instruction of the form "load reg,
[reg_addr+<offs>]", where reg_addr and dest can't be the same
register.

This caused the following verifier error:

*** Bad machine code: No live range at def ***
- function:    f3
- basic block: entry 0x9d68664 (BB#0) [0B;5056B)
- instruction: 3688B    %vreg96<earlyclobber,def> = LDDWRdPtrQ
<fi#0>, 0;
mem:LD2[FixedStack0](align=1) DREGS:%vreg96
- operand 0:   %vreg96<earlyclobber,def>
3688e is not live in [3688r,4480r:0)  0 at 3688r

*** Bad machine code: Early clobber def must be at an early-clobber slot ***
- function:    f3
Valno #0 is defined at 3688r in [3688r,4480r:0)  0 at 3688r

I've noticed this only happens when loading from frame indexes like in this
case, regular loads won't error.

Does anybody know what is causing this sort of error or if I'm missing
something obvious? I can provide any other debug info if requested.

Thanks in advance.
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20120714/21b52e28/attachment.html>

On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at gmail.com>
wrote:
> Hello,
> 
> I'm getting a machine verifier error after introducing the earlyclobber
constraint to some instructions where the src and dest regs can't be the
same. The offending instruction pattern is this one:
> 
> let canFoldAsLoad = 1,
> isReMaterializable = 1,
> Constraints = "@earlyclobber $dst" in
> def LDDWRdPtrQ : Inst<(outs DREGS:$dst),
>                         (ins memri:$src),
>                         "lddw\t$dst, $src",
>                         [(set DREGS:$dst, (load addr:$src))]>;
> 
> This is just a load with displacement instruction of the form "load
reg, [reg_addr+<offs>]", where reg_addr and dest can't be the
same register.
> 
> This caused the following verifier error:
> 
> *** Bad machine code: No live range at def ***
> - function:    f3
> - basic block: entry 0x9d68664 (BB#0) [0B;5056B)
> - instruction: 3688B    %vreg96<earlyclobber,def> = LDDWRdPtrQ
<fi#0>, 0; mem:LD2[FixedStack0](align=1) DREGS:%vreg96
> - operand 0:   %vreg96<earlyclobber,def>
> 3688e is not live in [3688r,4480r:0)  0 at 3688r
> 
> *** Bad machine code: Early clobber def must be at an early-clobber slot
***
> - function:    f3
> Valno #0 is defined at 3688r in [3688r,4480r:0)  0 at 3688r
> 
> I've noticed this only happens when loading from frame indexes like in
this case, regular loads won't error.
Spiller bug, should be fixed in r160219.

/jakob

Hello Jakob,

I'm still getting the error, I can give you any other debug info you need.
I haven't pasted the regalloc debug info here because it is quite huge, but
if you tell me what specific details you need I will include them.

Thanks for your help!

2012/7/14 Jakob Stoklund Olesen <stoklund at 2pi.dk>
>
> On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at gmail.com>
wrote:
>
> > Hello,
> >
> > I'm getting a machine verifier error after introducing the
earlyclobber
> constraint to some instructions where the src and dest regs can't be
the
> same. The offending instruction pattern is this one:
> >
> > let canFoldAsLoad = 1,
> > isReMaterializable = 1,
> > Constraints = "@earlyclobber $dst" in
> > def LDDWRdPtrQ : Inst<(outs DREGS:$dst),
> >                         (ins memri:$src),
> >                         "lddw\t$dst, $src",
> >                         [(set DREGS:$dst, (load addr:$src))]>;
> >
> > This is just a load with displacement instruction of the form
"load reg,
> [reg_addr+<offs>]", where reg_addr and dest can't be the
same register.
> >
> > This caused the following verifier error:
> >
> > *** Bad machine code: No live range at def ***
> > - function:    f3
> > - basic block: entry 0x9d68664 (BB#0) [0B;5056B)
> > - instruction: 3688B    %vreg96<earlyclobber,def> = LDDWRdPtrQ
<fi#0>,
> 0; mem:LD2[FixedStack0](align=1) DREGS:%vreg96
> > - operand 0:   %vreg96<earlyclobber,def>
> > 3688e is not live in [3688r,4480r:0)  0 at 3688r
> >
> > *** Bad machine code: Early clobber def must be at an early-clobber
slot
> ***
> > - function:    f3
> > Valno #0 is defined at 3688r in [3688r,4480r:0)  0 at 3688r
> >
> > I've noticed this only happens when loading from frame indexes
like in
> this case, regular loads won't error.
>
> Spiller bug, should be fixed in r160219.
>
> /jakob
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20120714/75aedd02/attachment.html>