search for: lddwrdptrq

...m getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]"...

...ier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr:$src))]>; > > This is just a load with displacement instruction of the form "load reg, [reg...

...rlyclobber > constraint to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > > let canFoldAsLoad = 1, > > isReMaterializable = 1, > > Constraints = "@earlyclobber $dst" in > > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > > (ins memri:$src), > > "lddw\t$dst, $src", > > [(set DREGS:$dst, (load addr:$src))]>; > > > > This is just a load with displacement instruction of the f...

...nt to some instructions where the src and dest regs can't be the >> same. The offending instruction pattern is this one: >> > >> > let canFoldAsLoad = 1, >> > isReMaterializable = 1, >> > Constraints = "@earlyclobber $dst" in >> > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), >> > (ins memri:$src), >> > "lddw\t$dst, $src", >> > [(set DREGS:$dst, (load addr:$src))]>; >> > >> > This is just a load with displacement...