search for: dreg

...quot;; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode, SDNo...

...quot;; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode, SDNo...

...gt; dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > multiclass BinaryOpMCInt...

...n tener que recurrir a ningún paquete de R adicional del tipo plyr, dplyr, etc. (no sé si esto es posible). EJEMPLO: require(data.table) DT <- data.table( id = rep(c(1,8,17),c(2,2,1)), start = as.Date(rep(c('2005-02-27','2006-07-17','2005-05-30'),c(2,2,1))), dreg = as.Date(c('2006-04-20','2007-02-19','2008-01-15','2008-01-29','2006-02-05')), valor = rep(c(24,15,32),c(2,2,1)), end = as.Date(rep(c('2007-05-15','2008-02-05','2007-12-31'),c(2,2,1))) ) id start dreg valor...

...gt; dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > multiclass BinaryOpMCInt...

...r error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]", where reg_addr and...

...the following piece of C code: struct ss { int a; int b; int c; }; void loop(struct ss *x, struct ss **y, int z) { int i; for (i=0; i<z; ++i) { x->c += y[i]->b; } } The problem relies in the register classes for the load and store with displacement instructions: - load DREGS:$dst, PTR:$p - store DREGS:$src, PTR:$p where DREGS is a regclass composed of 16 registers and PTR is a regclass composed of 2 registers, but the key point here is that PTR is a subset of DREGS, so cross class copies are perfectly allowed. One of the 2 registers in the PTR regclass is reserved for...

Hello Jim thanks for the reply, For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: def : Pat<(add DLDREGS:$src1, imm:$src2), (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; Now, the typical pattern concerning additions with global addresses looks like this: (taken from x86) def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), (ADD32ri GR32:$src1, tglo...

On Apr 26, 2011, at 1:27 PM, Borja Ferrer wrote: > Hello Jim thanks for the reply, > > For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: > def : Pat<(add DLDREGS:$src1, imm:$src2), > (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; > Cool. That's exactly the sort of thing I was referring to. > Now, the typical pattern concerning additions with global addresses looks like this: (taken from x86) > def : Pat<(add...

...the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr:$src))]>; > > This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]&q...

...Borja Ferrer wrote: > > > Hello Jim thanks for the reply, > > > > For normal additions with immediates I've done the same as ARM does, > basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in > the .td file like this: > > def : Pat<(add DLDREGS:$src1, imm:$src2), > > (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; > > > > Cool. That's exactly the sort of thing I was referring to. > > > > Now, the typical pattern concerning additions with global addresses looks > like this: (ta...

...ptimization or i missed something out here. This is for an out of tree backend im writing. I managed to reduce it to the following C function: void foo(int *a) // int here is 16bits { *a &= 0xFF; } This is the code before regalloc: Live Ins: %R25R24 %vreg0<def> = COPY %R25R24; DREGS:%vreg0 %vreg2<def> = COPY %vreg0; PTRREGS:%vreg2 DREGS:%vreg0 %vreg1<def> = LDWRd %vreg2; mem:LD2[%a](align=1)(tbaa=!"int") DLDREGS:%vreg1 PTRREGS:%vreg2 %vreg3<def> = ANDIWRdK %vreg1, 255; DLDREGS:%vreg3,%vreg1 %vreg5<def> = COPY %vreg0; PTRREGS:%...

...to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > > let canFoldAsLoad = 1, > > isReMaterializable = 1, > > Constraints = "@earlyclobber $dst" in > > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > > (ins memri:$src), > > "lddw\t$dst, $src", > > [(set DREGS:$dst, (load addr:$src))]>; > > > > This is just a load with displacement instruction of the form "load reg, &...

...t; int c; > }; > void loop(struct ss *x, struct ss **y, int z) > { > int i; > for (i=0; i<z; ++i) > { > x->c += y[i]->b; > } > } > > The problem relies in the register classes for the load and store with displacement instructions: > - load DREGS:$dst, PTR:$p > - store DREGS:$src, PTR:$p > where DREGS is a regclass composed of 16 registers and PTR is a regclass composed of 2 registers, but the key point here is that PTR is a subset of DREGS, so cross class copies are perfectly allowed. > One of the 2 registers in the PTR regclass...

...intf_json() includes a JSON array called 'expr'. > I would like to suggest that each type be split into its own object where > the 'type' value becomes the key name. So for example, rather than this: > > { > "type": "payload", > "dreg": 1, > "offset": 9, > "len": 1, > "base": "network" > }, > { > "type": "cmp", > "sreg": 1, > "op": "eq", > "data_reg": { > &qu...

...re the src and dest regs can't be the >> same. The offending instruction pattern is this one: >> > >> > let canFoldAsLoad = 1, >> > isReMaterializable = 1, >> > Constraints = "@earlyclobber $dst" in >> > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), >> > (ins memri:$src), >> > "lddw\t$dst, $src", >> > [(set DREGS:$dst, (load addr:$src))]>; >> > >> > This is just a load with displacement instruction of the fo...

...be expaneded to ld r1, P+ ld r2, P where "ld _, P+" is an instruction that loads a single byte from P, and post-increments P by one. How can I represent this behaviour in LLVM? Currently, I have let Constraints = "@earlyclobber $reg" in def LDWRdPtr : Pseudo<(outs DREGS:$reg), (ins PTRREGS:$ptrreg), "ldw\t$reg, $ptrreg", [(set i16:$reg, (load i16:$ptrreg))]>, Requires<[HasSRAM]>; The problem, of course, is that with this definition I end up with code...

...enVecExtract>; defm VEXTRACT : VectorExtract<IL_vextract>; // Class that handles the various vector extract patterns multiclass VectorExtract<SDNode OpNode> { ... def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>; ... } class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode> : ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1), "mov $dst, $src0", [(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>; class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern&g...

...re you primarily trying to avoid Expand being implemented as a lib call with a larger type? No - I’m stuck in this situation: - 8-bit addition is legal - 16-bit addition is illegal, should expand into an add and an add with carry - A few operations support 16-bit operands - the 16-bit DREGS register class The legalizer sees that 16-bit addition should expand. It sees that there is a 16-bit register class, and it sees that 16-bit values are legal. As 16-bit is legal, it does not try and expand into a smaller type (8-bit). This causes instruction selection to fail. I can see why...

Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean: DREGS: R31R30, R29R28 down to R1R0 (16 regs) DLDREGS: R31R30, R29R28 down to R17R16 (8 regs) PTRREGS: R31R30, R29R28, R27R26 (3 regs) All classes intersect each other giving as a result the smaller class: DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think...